SI5315 Datasheet, PDF (6/54 Pages) Silicon Laboratories – Provides jitter attenuation and frequency translation between SONET/PDH and Ethemet

Si5315
Table 2. DC Characteristics (Continued)
(V_DD = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, T_A = –40 to 85 ºC)
Parameter
Symbol
Test Condition
Min Typ Max Units
Output Drive Current
CKO_IO
CMOS
Driving into CKO_VOL for out-
put low or CKO_VOH for out-
put high. CKOUT+ and
CKOUT– shorted externally.
2-Level LVCMOS Input Pins
V_DD = 1.71 V
V_DD = 2.97 V
7.5
—
—
mA
32
—
—
mA
Input Voltage Low
V_IL
Input Voltage High
V_IH
Input Low Current
Input High Current
Weak Internal Input Pull-up
Resistor
I_IL
I_IH
R_PUP
V_DD = 1.71 V
V_DD = 2.25 V
V_DD = 2.97 V
V_DD = 1.89 V
V_DD = 2.25 V
V_DD = 3.63 V
—
—
0.5
V
—
—
0.7
V
—
—
0.8
V
1.4
—
—
V
1.8
—
—
V
2.5
—
—
V
—
—
50
µA
—
—
50
µA
—
75
—
k
Weak Internal Input
Pull-down Resistor
R_PDN
—
75
—
k
3-Level Input Pins
Input Voltage Low
V_ILL
—
— 0.15 x V_DD V
Input Voltage Mid
V_IMM
0.45 x V_DD — 0.55 x V_DD V
Input Voltage High
V_IHH
0.85 x V_DD —
—
V
Input Low Current
I_ILL
See note 3.
–20
—
—
µA
Input Mid Current
I_IMM
See note 3.
–2
—
2
µA
Input High Current
I_IHH
See note 3.
—
—
20
µA
Notes:
1. Refers to Si5315A speed grade.
2. Refers to Si5315B speed grade.
3. This is the amount of leakage that the 3L inputs can tolerate from an external driver. See Figure 3 on page 11.
6
Rev. 1.0