SI5315 Datasheet, PDF (34/54 Pages) Silicon Laboratories – Provides jitter attenuation and frequency translation between SONET/PDH and Ethemet

Si5315
6. High-Speed I/O
6.1. Input Clock Buffers
The Si5315 provides differential inputs for the CKINn clock inputs. These inputs are internally biased to a common
mode voltage [see Table 2, “DC Characteristics”] and can be driven by either a single-ended or differential source.
Figure 11 through Figure 14 show typical interface circuits for LVPECL, CML, LVDS, or CMOS input clocks. Note
that the jitter generation improves for higher levels on CKINn (within the limits in Table 3, “AC Characteristics”).
AC coupling the input clocks is recommended because it removes any issue with common mode input voltages.
However, either ac or dc coupling is acceptable. Figures 11 and 12 show various examples of different input
termination arrangements. Unused inputs can be left unconnected.
3.3 V
130  130 
C
LVPECL
Driver
82  82 
C
Si5315
40 k
40 k
CKIN +
300 
CKIN ^_
± ^VICM
Figure 11. Differential LVPECL Termination
3.3 V
130 
C
Driver
82 
C
Si5315
40 k
40 k
CKIN +
300 
CKIN ^_
± ^VICM
Figure 12. Single-ended LVPECL Termination
34
Rev. 1.0