SI5315 Datasheet, PDF (45/54 Pages) Silicon Laboratories – Provides jitter attenuation and frequency translation between SONET/PDH and Ethemet

Pin #
14
16
17
18
21
23
22
Pin Name
DBL2_BY
CKIN1+
CKIN1–
LOL
CS_CA
BWSEL1
BWSEL0
Si5315
Table 19. Si5315 Pin Descriptions (Continued)
I/O Signal Level
Description
I
3-Level Output 2 Disable/Bypass Mode Control.
Controls enable of CKOUT2 divider/output buffer path and
PLL bypass mode.
L = CKOUT2 enabled
M = CKOUT2 disabled
H = Bypass mode with CKOUT2 enabled. Bypass mode is
not supported with CMOS clock outputs (SFOUT = LH).
This pin has a weak pull-up and weak pull-down and defaults
to M.
Some designs may require an external resistor voltage
divider when driven by an active device that will tri-state.
I
Multi
Clock Input 1.
Differential input clock. This input can also be driven with a
single-ended signal. Input frequency selected from a table of
values. The same frequency must be applied to CKIN1 and
CKIN2.
O
LVCMOS PLL Loss of Lock Indicator.
This pin functions as the active high PLL loss of lock indica-
tor.
0 = PLL locked
1 = PLL unlocked
I/O LVCMOS Input Clock Select/Active Clock Indicator.
Input:
If manual clock selection mode is chosen
(AUTOSEL = L), this pin functions as the manual
input clock selector. This input is internally deglitched
to prevent inadvertent clock switching during
changes in the CS input state.
0 = Select CKIN1
1 = Select CKIN2
If configured as input, must be set high or low.
Output: If automatic clock selection mode is chosen
(AUTOSEL = M or H), this pin indicates which of the
two input clocks is currently the active clock. If
alarms exist on both CKIN1 and CKIN2, indicating
that the holdover state has been entered, CA will
indicate the last active clock that was used before
entering the hold state.
0 = CKIN1 active input clock
1 = CKIN2 active input clock
I
3-Level Loop Bandwidth Select.
Three level inputs that select the DSPLL closed loop band-
width. See Table 9 on page 20 for available settings.
These pins have both weak pull-ups and weak pull-downs
and default to M.
Some designs may require an external resistor voltage
divider when driven by an active device that will tri-state.
Rev. 1.0
45