SI5315 Datasheet, PDF (8/54 Pages) Silicon Laboratories – Provides jitter attenuation and frequency translation between SONET/PDH and Ethemet

Si5315
Table 3. AC Characteristics
(V_DD = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, T_A = –40 to 85 ºC)
Parameter
Symbol
Test Condition
Min Typ Max Units
Input Frequency
CKINn Input Pins
CKN_F
0.008 — 644.53 MHz
Input Duty Cycle (Minimum
Pulse Width)
CKN_DC
Whichever is smaller¹
40
—
60
%
2
—
—
ns
Input Capacitance
Input Rise/Fall Time
CKN_CIN
CKN_TRF
20–80%
See Figure 2
—
—
3
pF
—
—
11
ns
CKOUTn Output Pins
Output Frequency (Output not
configured for CMOS or disable) ^CK_OF
Note 2
Note 3
0.008 — 644.53 MHz
0.008 —
125 MHz
Maximum Output Frequency in CKO_FMC
CMOS Format
—
— 161.13 MHz
Output Rise/Fall (20–80%) at CKO_TRF Output not configured for CMOS —
230
350
ps
644.5313 MHz
or disabled, see Figure 2
Single Ended Output Rise/Fall
(20–80%)
CKO_TRF
CMOS Output
V_DD = 1.62
Cload = 5 pF
CMOS Output
V_DD = 2.97
Cload = 5 pF
—
—
8
ns
—
—
2
ns
Output Duty Cycle Differential
Uncertainty
CKO_DC
100  Load
Line to Line
Measured at 50% Point
(not for CMOS)
—
—
±40 ps
LVCMOS Pins
Input Capacitance
C_in
Notes:
1. Assumes N3 does not equal 1. IF N3 = 1, CKN_DC = 50 µs.
2. Refers to Si5315A speed grade.
3. Refers to Si5315B speed grade.
—
—
3
pF
8
Rev. 1.0