SI5315 Datasheet, PDF (18/54 Pages) Silicon Laboratories – Provides jitter attenuation and frequency translation between SONET/PDH and Ethemet

Si5315
4.2.3. Jitter Tolerance
Jitter tolerance is defined as the maximum peak-to-peak sinusoidal jitter that can be present on the incoming clock
before the DSPLL loses lock. The tolerance is a function of the jitter frequency, because tolerance improves for
lower input jitter frequency.
The jitter tolerance of the DSPLL is a function of the loop bandwidth setting. Figure 9 shows the general shape of
the jitter tolerance curve versus input jitter frequency. For jitter frequencies above the loop bandwidth, the tolerance
is a constant value A_j0. Beginning at the PLL bandwidth, the tolerance increases at a rate of 20 dB/decade for
lower input jitter frequencies.
Input
Jitter
Amplitude
A_j0
–20 dB/dec.
Excessive Input Jitter Range
BW/100 BW/10 BW
f_{Jitter In}
Figure 9. Jitter Tolerance Mask/Template
The equation for the high frequency jitter tolerance can be expressed as a function of the PLL loop bandwidth
(i.e., BW):
A_j0
=
5_----0_---0_----0_-
BW
ns pk-pk
For example, the jitter tolerance when f_in = 19.44 MHz, f_out = 161.13 MHz and the loop bandwidth (BW) is 113 Hz:
A_j0
=
5_----0_---0_----0_-
113
=
44.24
ns pk-pk
4.2.4. Jitter Attenuation Performance
The Internal VCO uses the reference clock on the XA/XB pins as its reference for jitter attenuation. The XA/XB pins
support either a crystal input or an input buffer single-ended or differential clock input, such that an external
oscillator can become the reference source. In either case, the device accepts a wide margin in absolute frequency
of the reference input. (See 5.5. "Holdover Mode" on page 32.) In holdover, the Si5315's output clock stability
matches the reference supplied on the XA/XB pins. The external crystal or reference clock must be selected based
on the stability requirements of the application if holdover is a key requirement.
However, care must be exercised in certain areas for optimum performance. For examples of connections to the
XA/XB pins, refer to 7. "Crystal/Reference Clock Input" on page 38.
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Rev. 1.0