SI5315 Datasheet, PDF (7/54 Pages) Silicon Laboratories – Provides jitter attenuation and frequency translation between SONET/PDH and Ethemet

Si5315
Table 2. DC Characteristics (Continued)
(V_DD = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, T_A = –40 to 85 ºC)
Parameter
Symbol
Test Condition
Min Typ Max Units
LVCMOS Output Pins
Output Voltage Low
V_OL
I_O = 2 mA
—
—
0.4
V
V_DD = 1.62 V
I_O = 2 mA
V_DD = 2.97 V
—
—
0.4
V
Output Voltage High
V_OH
I_O = –2 mA
V_DD – 0.4 —
—
V
V_DD = 1.62 V
I_O = –2 mA
V_DD – 0.4 —
—
V
V_DD = 2.97 V
Disabled Leakage Current
I_OZ
RST = 0
–100 —
100
µA
Single-Ended Reference Clock Input Pin XA (XB with Cap to Gnd)
Input Resistance
XA_RIN
XTAL/CLOCK = M
Input Voltage Level Limits
XA_VIN
Input Voltage Swing
XA_VPP
Differential Reference Clock Input Pins (XA/XB)
—
12
—
k
0
—
1.2
V
0.5
—
1.2
V_PP
Input Resistance
Differential Input Voltage
Level Limits
XA/XB_RIN
XA/XB_VIN
XTAL/CLOCK = M
—
12
—
k
0
—
1.2
V
Input Voltage Swing
XA_VPP/XB_VPP
0.5
—
2.4
V_PP
Notes:
1. Refers to Si5315A speed grade.
2. Refers to Si5315B speed grade.
3. This is the amount of leakage that the 3L inputs can tolerate from an external driver. See Figure 3 on page 11.
Rev. 1.0
7