SI5315 Datasheet, PDF (19/54 Pages) Silicon Laboratories – Provides jitter attenuation and frequency translation between SONET/PDH and Ethemet

Si5315
5. Frequency Plan Tables
For ease of use, the Si5315 is pin controlled to enable simple device configuration of the frequency plan and PLL
loop bandwidth via a predefined look up table. The DSPLL has been optimized for each frequency multiplication
and PLL loop bandwidth provided in Table 9 on page 20.
Many of the control inputs are three levels: High, Low, and Medium. High and Low are standard voltage levels
determined by the supply voltage: V_DD and Ground. If the input pin is left floating, it is driven to nominally half of
V_DD. Effectively, this creates three logic levels for these controls. See 1.2. "Three-Level (3L) Input Pins (With
External Resistors)" on page 12 and 8. "Power Supply Filtering" on page 41 for additional information.
5.1. Frequency Multiplication Plan
The input to output clock multiplication is set by the 3-level FRQSEL[3:0] pins. The device provides a wide range of
commonly used SyncE, SONET/SDH, and PDH frequency translations. The CKIN1 and CKIN2 inputs must be the
same frequency as specified in Table 9. Both CKOUT1 and CKOUT2 outputs are at the same frequency.
5.1.1. PLL Loop Bandwidth Plan
The Si5315's loop bandwidth ranges from 60 Hz to 8.4 kHz. For each frequency multiplication, its corresponding
loop bandwidth is provided in a simple look up table. (See Table 9 on page 20.) The loop bandwidth (BW) is
digitally programmable using the 3-level BWSEL [1:0] and FRQTBL input pins.
Rev. 1.0
19