SI5315 Datasheet, PDF (29/54 Pages) Silicon Laboratories – Provides jitter attenuation and frequency translation between SONET/PDH and Ethemet

Si5315
5.2. PLL Self-Calibration
An internal self-calibration (ICAL) is performed before operation to optimize loop parameters and jitter
performance. While the self-calibration is being performed, the DSPLL is being internally controlled by the self-
calibration state machine. The LOL alarm will be active during ICAL. The self-calibration time t_LOCKHW is given in
Table 3, “AC Characteristics”.
Any of the following events will trigger a self-calibration:
 Power-on-reset (POR)
 Release of the external reset pin RST (transition of RST from 0 to 1)
 Change in FRQSEL, FRQTBL, BWSEL, or XTAL/CLOCK pins
 Internal DSPLL registers out-of-range, indicating the need to relock the DSPLL
In any of the above cases, an internal self-calibration will be initiated if a valid input clock exists (no input alarm)
and is selected as the active clock at that time. The external crystal or reference clock must also be present for the
self-calibration to begin. If valid clocks are not present, the self-calibration state machine will wait until they appear,
at which time the calibration will start. An output clock will be active while waiting for a valid input clock. The output
clock frequency is based on the VCO range determine by FRQSEL and FRQTBL settings. This output clock will
vary by ±20%. If no output clock is desired prior to an ICAL, then the SFOUT pins should be kept at LM for
1.2 seconds until the output clock is stable.
After a successful self-calibration has been performed with a valid input clock, no subsequent self calibrations are
performed unless one of the above conditions are met. If the input clock is lost following self-calibration, the device
enters holdover mode. When the input clock returns, the device relocks to the input clock without performing a self-
calibration.
5.2.1. Input Clock Stability during Internal Self-Calibration
An exit from reset must occur when the selected CKINn clock is stable in frequency with a frequency value that is
within the device operating range. The other CKINs must also either be stable in frequency or squelched during a
reset.
5.2.2. Self-Calibration caused by Changes in Input Frequency
If the selected CKINn varies by 500 ppm or more in frequency since the last calibration, the device may initiate a
self-calibration.
5.2.3. Device Reset
Upon powerup, the device internally executes a power-on-reset (POR) which resets the internal device logic. The
pin RST can also be used to initiate a reset. The device stays in this state until a valid CKINn is present, when it
then performs a PLL Self-Calibration (See 5.2. "PLL Self-Calibration”).
5.2.4. Recommended Reset Guidelines
Follow the recommended RESET guidelines in Table 10 when reset should be applied to a device.
Table 10. Si5315 Pins and Reset
Pin #
2
11
22
23
24
25
26
27
Si5315 Pin Name
FRQTBL
XTAL/CLOCK
BWSEL0
BWSEL1
FRQSEL0
FRQSEL1
FRQSEL2
FRQSEL3
Must Reset after Changing
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Rev. 1.0
29