SI5315 Datasheet, PDF (10/54 Pages) Silicon Laboratories – Provides jitter attenuation and frequency translation between SONET/PDH and Ethemet

Si5315
Table 4. Jitter Generation
(V_DD = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, T_A = –40 to 85 ºC)
Parameter
Symbol _{Test Condition}^1,2,3,4
Min Typ Max
GR-253 Spec
Unit
Jitter Gen OC-192
Measuremen _{DSPLL BW}¹
t Filter (MHz)
0.02–80
167 Hz⁵
—
J_GEN
4–80
0.05–80
167 Hz⁵
—
167 Hz⁵
—
0.483 0.628
0.302 0.392
0.467 0.607
Jitter Gen OC-48
J_GEN
0.012–20
167 Hz⁵
111 Hz⁶
— 0.470 0.611
— 0.565 0.734
IEEE 802.3 GbE
RMS Jitter
J_GEN
1.875–20
83 Hz⁶
— 0.232 0.301
N/A
N/A
1.0 ps_rms
(0.01 UI_rms
4.02 ps_rms
(0.01 UI_rms)
4.02 ps_rms
(0.01 UI_rms)
ps_rms
ps_rms
ps_rms
ps_rms
ps_rms
ps_rms
Notes:
1. BWSEL [1:0] loop bandwidth settings provided in Table 9 on page 20.
2. 40 MHz fundamental mode crystal used as XA/XB input.
3. V_DD = 2.5 V
4. T_A = 85 °C
5. Si5315A test condition: f_IN = 19.44 MHz, f_OUT = 156.25 MHz, LVPECL clock input: 1.19 Vppd with 0.5 ns rise/fall time
(20–80%), LVPECL clock output.
6. Si5315B test condition: f_IN =19.44 MHz, f_OUT = 125 MHz, LVPECL clock input: 1.19 Vppd with 0.5 ns rise/fall time (20-
80%), LVPECL clock output.
V
SIGNAL +
Differential I/Os V_ICM , V_OCM
SIGNAL –
V_ISE , V_OSE
Single-Ended
Peak-to-Peak Voltage
(SIGNAL +) – (SIGNAL –)
V_ICM, V_OCM
SIGNAL +
SIGNAL –
V_ID,V_OD
Differential
Peak-to-Peak Voltage
t
V_ID = (SIGNAL+) – (SIGNAL–)
Figure 1. CKIN Voltage Characteristics
DOUT, CLOUT
t_F
t_R
Figure 2. Rise/Fall Time Characteristics
80%
20%
10
Rev. 1.0