C8051F85X86X Datasheet, PDF (80/290 Pages) Silicon Laboratories – Low-Cost 8-bit MCU Family with up to 8 kB of Flash

C8051F85x/86x
MUX Select
P0.x
R_MUX
RC_Input= R_MUX * C_SAMPLE
C_SAMPLE
Note: The value of CSAMPLE depends on the PGA Gain. See electrical specifications for details.
Figure 14.4. ADC0 Equivalent Input Circuits
14.2.5. Gain Setting
The ADC has gain settings of 1x and 0.5x. In 1x mode, the full scale reading of the ADC is determined directly by
VREF. In 0.5x mode, the full-scale reading of the ADC occurs when the input voltage is VREF x 2. The 0.5x gain
setting can be useful to obtain a higher input Voltage range when using a small VREF voltage, or to measure input
voltages that are between VREF and VDD. Gain settings for the ADC are controlled by the ADGN bit in register
ADC0CF. Note that even with a gain setting of 0.5, voltages above the supply rail cannot be measured directly by
the ADC.
14.3. 8-Bit Mode
Setting the ADC08BE bit in register ADC0CF to 1 will put the ADC in 8-bit mode.In 8-bit mode, only the 8 MSBs of
data are converted, allowing the conversion to be completed in fewer SAR clock cycles than a 10-bit conversion.
The two LSBs of a conversion are always 00 in this mode, and the ADC0L register will always read back 0x00.
14.4. 12-Bit Mode
When configured for 12-bit conversions, the ADC performs four 10-bit conversions using four different reference
voltages and combines the results into a single 12-bit value. Unlike simple averaging techniques, this method
provides true 12-bit resolution of AC or DC input signals without depending on noise to provide dithering. The
converter also employs a hardware dynamic element matching algorithm that reconfigures the largest elements of
the internal DAC for each of the four 10-bit conversions. This reconfiguration cancels any matching errors and
enables the converter to achieve 12-bit linearity performance to go along with its 12-bit resolution.
The 12-bit mode is enabled by setting the AD12BE bit in register ADC0AC to logic 1 and configuring the ADC in
burst mode (ADBMEN = 1) for four or more conversions. The conversion can be initiated using any of the
conversion start sources, and the 12-bit result will appear in the ADC0H and ADC0L registers. Since the 12-bit
result is formed from a combination of four 10-bit results, the maximum output value is 4 x (1023) = 4092, rather
than the max value of (2^12 – 1) = 4095 that is produced by a traditional 12-bit converter. To further increase
resolution, the burst mode repeat value may be configured to any multiple of four conversions. For example, if a
repeat value of 16 is selected, the ADC0 output will be a 14-bit number (sum of four 12-bit numbers) with 13
effective bits of resolution.
The AD12SM bit in register ADC0TK controls when the ADC will track and sample the input signal. When AD12SM
is set to 1, the selected input signal will be tracked before the first conversion of a set and held internally during all
four conversions. When AD12SM is cleared to 0, the ADC will track and sample the selected input before each of
the four conversions in a set. When maximum throughput (180-200 ksps) is needed, it is recommended that
AD12SM be set to 1 and ADTK to 0x3F, and that the ADC be placed in always-on mode (ADEN = 1). For sample
rates under 180 ksps, or when accumulating multiple samples, AD12SM should normally be cleared to 0, and
ADTK should be configured to provide the appropriate settling time for the subsequent conversions.
Preliminary Rev 0.6
83