C8051F85X86X Datasheet, PDF (200/290 Pages) Silicon Laboratories – Low-Cost 8-bit MCU Family with up to 8 kB of Flash

C8051F85x/86x
22.2. Power-Fail Reset / Supply Monitor
C8051F85x/86x devices have a supply monitor that is enabled and selected as a reset source after each power-on.
The supply monitor senses the voltage on the device VDD supply and can generate a reset if the supply drops
below the corresponding threshold. This monitor is enabled and enabled as a reset source after initial power-on to
protect the device until VDD is an adequate and stable voltage.
When enabled and selected as a reset source, any power down transition or power irregularity that causes VDD to
drop below the reset threshold will drive the RST pin low and hold the core in a reset state. When VDD returns to a
level above the reset threshold, the monitor will release the core from the reset state. The reset status can then be
read using the device reset sources module. After a power-fail reset, the PORF flag reads 1 and all of the other
reset flags in the RSTSRC Register are indeterminate. The power-on reset delay (t_POR) is not incurred after a
supply monitor reset. The contents of RAM should be presumed invalid after a VDD monitor reset.
The enable state of the VDD supply monitor and its selection as a reset source is not altered by device resets. For
example, if the VDD supply monitor is de-selected as a reset source and disabled by software, and then firmware
performs a software reset, the VDD supply monitor will remain disabled and de-selected after the reset.
To protect the integrity of flash contents, the VDD supply monitor must be enabled and selected as a reset source
if software contains routines that erase or write flash memory. If the VDD supply monitor is not enabled, any erase
or write performed on flash memory will be ignored.
Reset Threshold
(V_RST)
VDD
t
RST
VDD Monitor
Reset
Figure 22.3. VDD Supply Monitor Threshold
22.3. Enabling the VDD Monitor
The VDD supply monitor is enabled by default. However, in systems which disable the supply monitor, it must be
enabled before selecting it as a reset source. Selecting the VDD supply monitor as a reset source before it has
stabilized may generate a system reset. In systems where this reset would be undesirable, a delay should be
introduced between enabling the VDD supply monitor and selecting it as a reset source. No delay should be
introduced in systems where software contains routines that erase or write flash memory. The procedure for
enabling the VDD supply monitor and selecting it as a reset source is:
1. Enable the VDD supply monitor (VMONEN = 1).
2. Wait for the VDD supply monitor to stabilize (optional).
3. Enable the VDD monitor as a reset source in the RSTSRC register.
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