C8051F85X86X Datasheet, PDF (177/290 Pages) Silicon Laboratories – Low-Cost 8-bit MCU Family with up to 8 kB of Flash

C8051F85x/86x
Registers XBR0, XBR1 and XBR2 are used to assign the digital I/O resources to the physical I/O port pins. Note
that when the SMBus is selected, the crossbar assigns both pins associated with the SMBus (SDA and SCL);
when UART0 is selected, the crossbar assigns both pins associated with UART0 (TX and RX). UART0 pin
assignments are fixed for bootloading purposes: UART0 TX is always assigned to P0.4; UART0 RX is always
assigned to P0.5. Standard port I/Os appear contiguously after the prioritized functions have been assigned.
Figure 21.3 shows an example of the resulting pin assignments of the device with UART0 and SPI0 enabled and
the EXTCLK (P0.3) pin skipped (P0SKIP = 0x08). UART0 is the highest priority and it will be assigned first. The
UART0 pins can only appear on P0.4 and P0.5, so that is where it is assigned. The next-highest enabled peripheral
is SPI0. P0.0, P0.1 and P0.2 are free, so SPI0 takes these three pins. The fourth pin, NSS, is routed to P0.6
because P0.3 is skipped and P0.4 and P0.5 are already occupied by the UART. The other pins on the device are
available for use as general-purpose digital I/O or analog functions.
Port
P0
P1
P2
Pin Number 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1
SOIC-16 Package
QFN-20 Package
QSOP-24 Package
UART0-TX
UART0-RX
SPI0-SCK
SPI0-MISO
SPI0-MOSI
SPI0-NSS*
SMB0-SDA
SMB0-SCL
CMP0-CP0
CMP0-CP0A
CMP1-CP1
CMP1-CP1A
SYSCLK
PCA0-CEX0
PCA0-CEX1
PCA0-CEX2
PCA0-ECI
Timer0-T0
Timer1-T1
Timer2-T2
0001000000000000
Pin Skip Settings
P0SKIP
P1SKIP
The crossbar peripherals are assigned in priority order from top to bottom.
These boxes represent Port pins which can potentially be assigned to a peripheral.
Special Function Signals are not assigned by the crossbar. When these signals are
enabled, the Crossbar should be manually configured to skip the corresponding port pins.
Pins can be “skipped” by setting the corresponding bit in PnSKIP to 1.
* NSS is only pinned out when the SPI is in 4-wire mode.
Figure 21.3. Crossbar Priority Decoder Example
Note: The SPI can be operated in either 3-wire or 4-wire modes, pending the state of the NSSMD1–NSSMD0 bits
in register SPI0CN. According to the SPI mode, the NSS signal may or may not be routed to a port pin. The order
in which SMBus pins are assigned is defined by the SWAP bit in the SMB0TC register.
Preliminary Rev 0.6
183