C8051F85X86X Datasheet, PDF (240/290 Pages) Silicon Laboratories – Low-Cost 8-bit MCU Family with up to 8 kB of Flash

C8051F85x/86x
Register 24.3. SMB0CN: SMBus0 Control
Bit
7
6
5
4
3
2
1
0
Name MASTER TXMODE
STA
STO
ACKRQ ARBLOST ACK
SI
Type
R
R
RW
RW
R
R
RW
RW
Reset
0
0
0
0
0
0
0
0
SFR Address: 0xC0 (bit-addressable)
Table 24.9. SMB0CN Register Bit Descriptions
Bit
Name
Function
7
MASTER SMBus0 Master/Slave Indicator.
This read-only bit indicates when the SMBus0 is operating as a master.
0: SMBus0 operating in slave mode.
1: SMBus0 operating in master mode.
6
TXMODE SMBus0 Transmit Mode Indicator.
This read-only bit indicates when the SMBus0 is operating as a transmitter.
0: SMBus0 in Receiver Mode.
1: SMBus0 in Transmitter Mode.
5
STA
SMBus0 Start Flag.
When reading STA, a 1 indicates that a start or repeated start condition was detected on
the bus.
Writing a 1 to the STA bit initiates a start or repeated start on the bus.
4
STO
SMBus0 Stop Flag.
When reading STO, a 1 indicates that a stop condition was detected on the bus (in slave
mode) or is pending (in master mode).
When acting as a master, writing a 1 to the STO bit initiates a stop condition on the bus.
This bit is cleared by hardware.
3
ACKRQ SMBus0 Acknowledge Request.
0: No ACK requested.
1: ACK requested.
2
ARBLOST SMBus0 Arbitration Lost Indicator.
0: No arbitration error.
1: Arbitration error occurred.
1
ACK
SMBus0 Acknowledge.
When read as a master, the ACK bit indicates whether an ACK (1) or NACK (0) is
received during the most recent byte transfer.
As a slave, this bit should be written to send an ACK (1) or NACK (0) to a master
request. Note that the logic level of the ACK bit on the SMBus interface is inverted from
the logic of the register ACK bit.
Preliminary Rev 0.6
247