C8051F85X86X Datasheet, PDF (73/290 Pages) Silicon Laboratories – Low-Cost 8-bit MCU Family with up to 8 kB of Flash

C8051F85x/86x
13.1.2. Stop Mode
Setting the Stop Mode Select bit (PCON.1) causes the controller core to enter Stop mode as soon as the
instruction that sets the bit completes execution. Before entering stop mode, the system clock must be sourced by
the internal high-frequency oscillator. In stop mode the internal oscillator, CPU, and all digital peripherals are
stopped; the state of the external oscillator circuit is not affected. Each analog peripheral (including the external
oscillator circuit) may be shut down individually prior to entering stop mode. Stop mode can only be terminated by
an internal or external reset. On reset, the device performs the normal reset sequence and begins program
execution at address 0x0000.
If enabled, the Missing Clock Detector will cause an internal reset and thereby terminate the stop mode. The
Missing Clock Detector should be disabled if the CPU is to be put to in STOP mode for longer than the MCD
timeout.
13.2. LDO Regulator
C8051F85x/86x devices include an internal regulator that regulates the internal core and logic supply. Under
default conditions, the internal regulator will remain on when the device enters STOP mode. This allows any
enabled reset source to generate a reset for the device and bring the device out of STOP mode. For additional
power savings, the STOPCF bit can be used to shut down the regulator and the internal power network of the
device when the part enters STOP mode. When STOPCF is set to 1, the RST pin and a full power cycle of the
device are the only methods of generating a reset.
13.3. Power Control Registers
Register 13.1. PCON: Power Control
Bit
7
Name
Type
Reset
0
SFR Address: 0x87
Bit
Name
7:2
GF
1
STOP
0
IDLE
6
5
4
3
2
1
0
GF
STOP
IDLE
RW
RW
RW
0
0
0
0
0
0
0
Table 13.1. PCON Register Bit Descriptions
Function
General Purpose Flags 5-0.
These are general purpose flags for use under software control.
Stop Mode Select.
Setting this bit will place the CIP-51 in Stop mode. This bit will always be read as 0.
Idle Mode Select.
Setting this bit will place the CIP-51 in Idle mode. This bit will always be read as 0.
Preliminary Rev 0.6
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