C8051F85X86X Datasheet, PDF (206/290 Pages) Silicon Laboratories – Low-Cost 8-bit MCU Family with up to 8 kB of Flash

C8051F85x/86x
Table 22.5. RSTSRC Register Bit Descriptions
Bit
Name
Function
4
SWRSF Software Reset Force and Flag.
Read: This bit reads 1 if last reset was caused by a write to SWRSF.
Write: Writing a 1 to this bit forces a system reset.
3
WDTRSF Watchdog Timer Reset Flag.
This read-only bit is set to 1 if a watchdog timer overflow caused the last reset.
2
MCDRSF Missing Clock Detector Enable and Flag.
Read: This bit reads 1 if a missing clock detector timeout caused the last reset.
Write: Writing a 1 to this bit enables the missing clock detector. The MCD triggers a reset
if a missing clock condition is detected.
1
PORSF Power-On / Supply Monitor Reset Flag, and Supply Monitor Reset Enable.
Read: This bit reads 1 anytime a power-on or supply monitor reset has occurred.
Write: Writing a 1 to this bit enables the supply monitor as a reset source.
0
PINRSF HW Pin Reset Flag.
This read-only bit is set to 1 if the RST pin caused the last reset.
Notes:
1. Reads and writes of the RSTSRC register access different logic in the device. Reading the register always returns
status information to indicate the source of the most recent reset. Writing to the register activates certain options as
reset sources. It is recommended to not use any kind of read-modify-write operation on this register.
2. When the PORSF bit reads back 1 all other RSTSRC flags are indeterminate.
3. Writing 1 to the PORSF bit when the supply monitor is not enabled and stabilized may cause a system reset.
Supply Monitor Control Registers
Register 22.6. VDM0CN: Supply Monitor Control
Bit
7
6
5
4
3
2
1
0
Name VDMEN VDDSTAT
Reserved
Type
RW
R
R
Reset
X
X
X
X
X
X
X
X
SFR Address: 0xFF
Table 22.6. VDM0CN Register Bit Descriptions
Bit
Name
Function
7
VDMEN Supply Monitor Enable.
This bit turns the supply monitor circuit on/off. The supply monitor cannot generate sys-
tem resets until it is also selected as a reset source in register RSTSRC. Selecting the
supply monitor as a reset source before it has stabilized may generate a system reset. In
systems where this reset would be undesirable, a delay should be introduced between
enabling the supply monitor and selecting it as a reset source.
0: Supply Monitor Disabled.
1: Supply Monitor Enabled.
212
Preliminary Rev 0.6