C8051F85X86X Datasheet, PDF (251/290 Pages) Silicon Laboratories – Low-Cost 8-bit MCU Family with up to 8 kB of Flash

C8051F85x/86x
25.2.2. 8-bit Timers with Auto-Reload
When TnSPLIT is set, the timer operates as two 8-bit timers (TMRnH and TMRnL). Both 8-bit timers operate in
auto-reload mode as shown in Figure 25.5. TMRnRLL holds the reload value for TMRnL; TMRnRLH holds the
reload value for TMRnH. The TRn bit in TMRnCN handles the run control for TMRnH. TMRnL is always running
when configured for 8-bit auto-reload mode.
Each 8-bit timer may be configured to clock from SYSCLK, SYSCLK divided by 12, or the external oscillator clock
source divided by 8. The Clock Select bits (TnMH and TnML in CKCON) select either SYSCLK or the clock defined
by the External Clock Select bit (TnXCLK in TMRnCN), as follows:
TnMH
0
0
1
TnXCLK
0
1
X
TMRnH Clock Source
SYSCLK / 12
External Clock / 8
SYSCLK
TnML
0
0
1
TnXCLK
0
1
X
TMRnL Clock Source
SYSCLK / 12
External Clock / 8
SYSCLK
The TFnH bit is set when TMRnH overflows from 0xFF to 0x00; the TFnL bit is set when TMRnL overflows from
0xFF to 0x00. When timer interrupts are enabled, an interrupt is generated each time TMRnH overflows. If tmier
interrupts are enabled and TFnLEN is set, an interrupt is generated each time either TMRnL or TMRnH overflows.
When TFnLEN is enabled, software must check the TFnH and TFnL flags to determine the source of the timer
interrupt. The TFnH and TFnL interrupt flags are not cleared by hardware and must be manually cleared by
software.
TnXCLK
SYSCLK / 12
0
External Clock / 8
1
SYSCLK
TnMH
0
TRn
1
TnML
TMRnRLH ^Reload
TCLK _TMRnH
TFnH
Overflow
TMRnRLL ^Reload
TFnLEN
Interrupt
1
TCLK _TMRnL
0
Figure 25.5. 8-Bit Mode Block Diagram
TFnL
Overflow
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Preliminary Rev 0.6