C8051F85X86X Datasheet, PDF (16/290 Pages) Silicon Laboratories – Low-Cost 8-bit MCU Family with up to 8 kB of Flash

C8051F85x/86x
Table 1.10. Comparators
Parameter
Positive Hysterisis
Mode 3 (CPnMD = 11)
Negative Hysterisis
Mode 3 (CPnMD = 11)
Input Range (CP+ or CP–)
Input Pin Capacitance
Common-Mode Rejection Ratio
Power Supply Rejection Ratio
Input Offset Voltage
Input Offset Tempco
Symbol
HYS_CP+
HYS_CP-
V_IN
C_CP
CMRR_CP
PSRR_CP
V_OFF
TC_OFF
Test Condition
CPnHYP = 00
CPnHYP = 01
CPnHYP = 10
CPnHYP = 11
CPnHYN = 00
CPnHYN = 01
CPnHYN = 10
CPnHYN = 11
T_A = 25 °C
Min
—
—
—
—
—
—
—
—
-0.25
—
—
—
-10
—
Typ
Max Unit
1.5
—
mV
4
—
mV
8
—
mV
16
—
mV
-1.5
—
mV
–4
—
mV
–8
—
mV
–16
—
mV
— V_DD+0.2 V
5
7.5
—
pF
70
—
dB
72
—
dB
0
10
mV
3.5
—
µV/°C
Table 1.11. Port I/O
Parameter
Symbol
Test Condition
Min
Typ
Output High Voltage (High Drive)
V_OH
Output Low Voltage (High Drive)
V_OL
Output High Voltage (Low Drive)
V_OH
Output Low Voltage (Low Drive)
V_OL
Input High Voltage
V_IH
Input Low Voltage
V_IL
Pin Capacitance
C_IO
Weak Pull-Up Current
I_PU
(V_IN = 0 V)
Input Leakage 
I_LK
(Pullups off or Analog)
I_OH = –3 mA
I_OL = 8.5 mA
I_OH = –1 mA
I_OL = 1.4 mA
V_DD = 3.6
GND < V_IN < V_DD
V_DD – 0.7
—
—
—
V_DD – 0.7
—
—
—
V_DD – 0.6
—
—
—
—
7
–30
–20
–1
—
Input Leakage Current with V_IN
I_LK
V_DD < V_IN < V_DD+2.0 V
0
5
above V_DD
Max
—
0.6
—
0.6
—
0.6
—
–10
1
150
Unit
V
V
V
V
V
V
pF
µA
µA
µA
16
Preliminary Rev 0.6