SI53315 Datasheet, PDF (7/30 Pages) Silicon Laboratories – 1:10 LOW JITTER UNIVERSAL BUFFER/LEVEL

Si53315
Table 9. AC Characteristics
(V_DD = 1.8 V 5%, 2.5 V  5%, or 3.3 V 10%,T_A = –40 to 85 C)
Parameter
Frequency
Symbol
Test Condition
Min
F
LVPECL, low power LVPECL,
1
LVDS, CML, HCSL
Typ
Max
Unit
—
1250
MHz
LVCMOS
1
—
200
MHz
Duty Cycle
D_C
200 MHz, 50 toV_DD/220/80% TBD
TBD
TBD
%
Note: 50% input duty
T_R/T_F<10% of period (LVCMOS)
cycle.
20/80% T_R/T_F<10% of period
48
50
52
%
(Differential)
Minimum Input Clock
Slew Rate¹
Output Rise/Fall Time
SR
T_R/T_F
Required to meet prop delay and
additive jitter specifications
(20–80%)
LVPECL, LVDS, CML, HCSL,
20/80%
200 MHz, 50 20/80%,
2 pF load (LVCMOS)
0.75
TBD
—
—
350
TBD
750
V/ns
ps
ps
Minimum Input Pulse
T_W
Width
500
—
—
ps
Additive Jitter
(Differential Clock
Input)
J
V_DD = 2.5/3.3 V, LVPECL/LVDS,
—
60
80
fs
F = 725 MHz, 0.75 V/ns
input slew rate
Propagation Delay
T_PLH,
T_PHL
Output Enable Time²
T_EN
Low to high, high to low
Single-ended
Low to high, high to low
Differential
F = 1 MHz
F = 100 MHz
TBD
TBD
—
—
—
TBD
ns
—
TBD
ns
2
—
s
60
—
ns
Output Disable Time² T_DIS
F = 725 MHz
F = 1 MHz
F = 100 MHz
F = 725 MHz
—
50
—
ns
—
2
—
s
—
25
—
ns
—
15
—
ns
Notes:
1. For clock division applications, a minimum input clock slew rate of 30 mV/ns is required.
2. See Figure 4.
3. Defined as skew between outputs on different devices operating at the same supply voltages, temperatures, and equal
load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.
4. Measured for 156.25 MHz carrier frequency. Sine-wave noise added to V_DDOX (1.8 V = 50 mV_PP,
2.5/3.3 V = 100 mV_PP) and noise spur amplitude measured. See AN491 for further details.
Preliminary Rev. 0.4
7