SI53315 Datasheet, PDF (24/30 Pages) Silicon Laboratories – 1:10 LOW JITTER UNIVERSAL BUFFER/LEVEL

Si53315
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GND
Pad
Q6
Q5
Q5
CLK_SEL
Table 18. Pin Description (Continued)
Output clock 6
Output clock 5 (complement)
Output clock 5
MUX input select pin (LVCMOS)
When CLK_SEL is high, CLK1 is selected
When CLK_SEL is low, CLK0 is selected
CLK_SEL contains an internal pull-down resistor
Q4
Q4
Q3
Q3
V_DDOA
GND
Output clock 4 (complement)
Output clock 4
Output clock 3 (complement)
Output clock 3
Output voltage supply – Bank A (Outputs Q0 to Q4)
Bypass with 1.0 µF capacitor and place as close to V_DDOA pin as possible.
Ground Pad
Power supply ground and thermal relief
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Preliminary Rev. 0.4