SI53315 Datasheet, PDF (10/30 Pages) Silicon Laboratories – 1:10 LOW JITTER UNIVERSAL BUFFER/LEVEL

Si53315
2. Functional Description
The Si53315 is a low jitter, low skew 1:10 differential buffer with an integrated 2:1 input mux and individual OE
control. The device has a universal input that accepts most common differential or LVCMOS input signals. A clock
select pin is used to select the active input clock. The selected clock input is routed to two independent banks of
outputs. Each output bank features control pins to select signal format and LVCMOS drive strength settings. In
addition, each clock output has an independent OE pin for individual clock enable/disable.
2.1. Universal, Any-Format Input
The Si53315 has a universal input stage that enables simple interfacing to a wide variety of clock formats, including
LVPECL, LVCMOS, LVDS, HCSL, and CML. Tables 12 and 13 summarize the various input ac- and dc-coupling
options supported by the device. Figures 1 and 2 show the recommended input clock termination options.
Table 12. LVPECL, LVCMOS, and LVDS
1.8 V
2.5/3.3 V
LVPECL
AC-Couple DC-Couple
N/A
N/A
Yes
Yes
LVCMOS
AC-Couple DC-Couple
No
Yes
No
Yes
LVDS
AC-Couple DC-Couple
Yes
No
Yes
Yes
1.8 V
2.5/3.3 V
Table 13. HCSL and CML
HCSL
AC-Couple DC-Couple
CML
AC-Couple DC-Couple
No
No
Yes
No
No
Yes (3.3 V)
Yes
No
0.1 uF
CLKx
Si533xx
100
/CLKx
0.1 uF
Figure 1. Differential LVPECL, LVDS, CML AC-Coupled Input Termination
VDDO _{= 3.3V, 2.5V, 1.8V}
CMOS
Rs
D riv e r
50
N o te : V D D O a n d V DD m u s t b e a t th e s a m e v o lta g e le v e l.
V DD
CLKx
0.1 uF
/C L K x
VREF
S i5 3 3 x x
Figure 2. LVCMOS DC-Coupled Input Termination
10
Preliminary Rev. 0.4