SI53315 Datasheet, PDF (12/30 Pages) Silicon Laboratories – 1:10 LOW JITTER UNIVERSAL BUFFER/LEVEL

Si53315
2.2. Input Bias Resistors
Internal bias resistors ensure a differential output low condition in the event that the clock inputs are not connected.
The noninverting input is biased with a 18.75 k pulldown to GND and a 75 k pullup to V_DD. The inverting input is
biased with a 75 k pullup to V_DD.
V_DD
R_PU
R_PU
+
R_PD
CLK0 or
CLK1
–
R_PU = 75 kohm
R_PD = 18.75 kohm
Figure 4. Input Bias Resistors
2.3. Universal, Any-Format Output Buffer
The Si53315 has highly flexible output drivers that support a wide range of clock signal formats, including LVPECL,
low power LVPECL, LVDS, CML, HCSL, and LVCMOS. SFOUT[0] and SFOUT[1] are 3-level inputs that can be
pin-strapped to select the clock signal formats for all of the outputs, Q0 through Q9. This feature enables the device
to be used for format/level translation in addition to clock distribution, minimizing the number of unique buffer part
numbers required in a typical application and simplifying design reuse. For EMI reduction applications, four
LVCMOS drive strength options are available for each V_DDO setting.
Table 14. Output Signal Format Selection
SFOUT[1]
Open*
SFOUT[0]
Open*
V_DDOX = 3.3 V
LVPECL
V_DDOX = 2.5 V
LVPECL
V_DDOX = 1.8 V
N/A
0
0
LVDS
LVDS
LVDS
0
1
LVCMOS, 24 mA drive LVCMOS, 18 mA drive LVCMOS, 12 mA drive
1
0
LVCMOS, 18 mA drive LVCMOS, 12 mA drive LVCMOS, 9 mA drive
1
1
LVCMOS, 12 mA drive LVCMOS, 9 mA drive
LVCMOS, 6 mA drive
Open*
0
LVCMOS, 6 mA drive LVCMOS, 4 mA drive
LVCMOS, 2 mA drive
Open*
1
LVPECL Low power LVPECL Low power
N/A
0
Open*
CML
CML
CML
1
Open*
HCSL
HCSL
HCSL
*Note: SFOUT[1:0] are 3-level input pins. Tie low for “0” setting. Tie high for “1” setting. When left open, the pin floats to
V_DD/2.
12
Preliminary Rev. 0.4