SI53315 Datasheet, PDF (21/30 Pages) Silicon Laboratories – 1:10 LOW JITTER UNIVERSAL BUFFER/LEVEL

3. Pin Description: 44-Pin QFN
Si53315
OE2 ¹
SFOUT[0] 2
OE1 ³
Q2 ⁴
Q2 ⁵
GND ⁶
Q1 ⁷
Q1 ⁸
Q0 ⁹
Q0 ¹⁰
OE0 ¹¹
GND
PAD
33 _OE7
32 SFOUT[1]
31 _OE8
30 _Q7
29 _Q7
28 _NC
27 Q8
26 _Q8
25 _Q9
24 _Q9
23 _OE9
Pin #
1
2
3
4
5
6
7
Name
OE2
SFOUT[0]
OE1
Q2
Q2
GND
Q1
Table 18. Pin Description
Description
Output enable—Output 2
When OE = high, the Q2 is enabled.
When OE = low, Q is held low, and Q is held high for differential formats.
For LVCMOS, both Q and Q are held low when OE is set low.
OE2 contains an internal pull-up resistor.
Output signal format control pin [0]
Three-level input control. Internally biased at V_DD/2. Can be left floating or tied to
ground or V_DD.
Output enable—Output 1
When OE = high, the Q1 is enabled.
When OE = low, Q is held low, and Q is held high for differential formats.
For LVCMOS, both Q and Q are held low when OE is set low.
OE1 contains an internal pull-up resistor.
Output clock 2 (complement)
Output clock 2
Ground
Output clock 1 (complement)
Preliminary Rev. 0.4
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