SI53315 Datasheet, PDF (13/30 Pages) Silicon Laboratories – 1:10 LOW JITTER UNIVERSAL BUFFER/LEVEL

Si53315
2.4. Input Mux and Output Enable Logic
The Si53315 provides two clock inputs for applications that need to select between one of two clock sources. The
CLK_SEL pin selects the active clock input. The table below summarizes the input and output clock based on the
input mux and output enable pin settings.
Table 15. Input Mux and Output Enable Logic
CLK_SEL CLK0
CLK1
OE¹
Q²
L
L
X
H
L
L
H
X
H
H
H
X
L
H
L
H
X
H
H
H
X
X
X
L
L³
Notes:
1. Output enable active high
2. On the next negative transition of CLK0 or CLK1.
3. Single-end: Q=low, Q=high
Differential: Q=low, Q=high
2.5. Power Supply (V_DD and V_DDOX)
The device includes separate core (V_DD) and output driver supplies (V_DDOX). This feature allows the core to
operate at a lower voltage than V_DDO, reducing current consumption in mixed supply applications. The core V_DD
supports 3.3, 2.5, or 1.8 V. Each output bank has its own V_DDOX supply, supporting 3.3, 2.5, or 1.8 V.
Preliminary Rev. 0.4
13