SI53315 Datasheet, PDF (22/30 Pages) Silicon Laboratories – 1:10 LOW JITTER UNIVERSAL BUFFER/LEVEL

Si53315
8
Q1
9
Q0
10
Q0
11
OE0
12
V_DD
13
OE3
14
CLK0
15
CLK0
Table 18. Pin Description (Continued)
Output clock 1
Output clock 0 (complement)
Output clock 0
Output enable—Output 0
When OE = high, the Q0 is enabled.
When OE = low, Q is held low, and Q is held high for differential formats.
For LVCMOS, both Q and Q are held low when OE is set low.
OE0 contains an internal pull-up resistor.
Core voltage supply
Bypass with 1.0 µF capacitor and place close to the V_DD pin as possible
Output Enable 3
When OE = high, the Q3 is enabled.
When OE = low, Q is held low, and Q is held high for differential formats.
For LVCMOS, both Q and Q are held low when OE is set low.
OE3 contains an internal pull-up resistor.
Input clock 0
Input clock 0 (complement)
When CLK0 is driven by a single-ended input, connect V_REF to CLK0.
CLK0 contains an internal pull-up resistor.
16
OE4
Output Enable 4
When OE = high, Q4 is enabled.
When OE = low, Q is held low, and Q is held high for differential formats.
For LVCMOS, both Q and Q are held low when OE is set low.
OE4 contains an internal pull-up resistor.
17
V_REF
Input reference voltage
When driven by a LVCMOS clock input, connect the unused clock input to V_REF and a
0.1 µF cap to ground. When driven by a differential clock, do not connect the V_REF pin.
18
OE5
Output Enable 5
When OE = high, Q5 is enabled.
When OE = low, Q is held low, and Q is held high for differential formats.
For LVCMOS, both Q and Q are held low when OE is set low.
OE5 contains an internal pull-up resistor.
19
CLK1
Input clock 1
22
Preliminary Rev. 0.4