SI53315 Datasheet, PDF (23/30 Pages) Silicon Laboratories – 1:10 LOW JITTER UNIVERSAL BUFFER/LEVEL

Si53315
Table 18. Pin Description (Continued)
20
CLK1
Input clock 1 (complement)
When CLK1 is driven by a single-ended input, connect V_REF to CLK1.
CLK1 contains an internal pull-up resistor
21
OE6
Output Enable 6
When OE = high, Q6 is enabled.
When OE = low, Q is held low, and Q is held high for differential formats.
For LVCMOS, both Q and Q are held low when OE is set low.
OE6 contains an internal pull-up resistor.
22
GND
Ground
23
OE9
Output Enable 9
When OE = high, the Output 9 outputs are enabled.
When OE = low, Q is held low, and Q is held high for differential formats.
For LVCMOS, both Q and Q are held low when OE is set low.
OE9 contains an internal pull-up resistor.
24
Q9
Output clock 9 (complement)
25
Q9
Output clock 9
26
Q8
Output clock 8 (complement)
27
Q8
Output clock 8
28
NC
No Connect
29
Q7
Output clock 7 (complement)
30
Q7
Output clock 7
31
OE8
Output Enable 8
When OE = high, Q8 is enabled.
When OE = low, Q is held low, and Q is held high for differential formats.
For LVCMOS, both Q and Q are held low when OE is set low.
OE8 contains an internal pull-up resistor.
32
SFOUT[1] Output signal format control pin [1]
Three-level input control. Internally biased at V_DD/2. Can be left floating or tied to
ground or V_DD.
33
OE7
Output Enable 7
When OE = high, Q7 is enabled.
When OE = low, Q is held low, and Q is held high for differential formats.
For LVCMOS, both Q and Q are held low when OE is set low.
OE7 contains an internal pull-up resistor.
34
V_DDOB
Output voltage supply – Bank B (Outputs Q5 through Q9)
Bypass with 1.0 µF capacitor and place as close to V_DDOB pin as possible.
35
Q6
Output clock 6 (complement)
Preliminary Rev. 0.4
23