SI53315 Datasheet, PDF (1/30 Pages) Silicon Laboratories – 1:10 LOW JITTER UNIVERSAL BUFFER/LEVEL

Si53315
1:10 LOW JITTER UNIVERSAL BUFFER/LEVEL
TRANSLATOR WITH 2:1 INPUT MUX AND INDIVIDUAL OE (<1.25 GHZ)
Features
 10 differential or 20 LVCMOS outputs Low propagation delay variation:
 Ultra-low additive jitter: 100 fs rms
<400 ps
 Wide frequency range:
1 MHz to 1.25 GHz
 Independent V_DD and V_DDO :
1.8/2.5/3.3 V
 Any-format input with pin selectable  Excellent power supply noise
output formats: LVPECL, Low Power rejection (PSRR)
LVPECL, LVDS, CML, HCSL,
LVCMOS
 Selectable LVCMOS drive strength to
tailor jitter and EMI performance
 2:1 mux with hot-swappable inputs _{ Small size: 44-QFN (7 mm x 7 mm)}
 Asynchronous output enable
 RoHS compliant, Pb-free
 Individual output enable
 Industrial temperature range:
 Low output-output skew: <50 ps
–40 to +85 °C
Applications
 High-speed clock distribution
 Ethernet switch/router
 Optical Transport Network (OTN)
 SONET/SDH
 PCI Express Gen 1/2/3
 Storage
 Telecom
 Industrial
 Servers
 Backplane clock distribution
Description
The Si53315 is an ultra low jitter ten output differential buffer with pin-selectable
output clock signal format and individual OE. The Si53315 features a 2:1 mux,
making it ideal for redundant clocking applications. The Si53315 utilizes Silicon
Laboratories' advanced CMOS technology to fanout clocks from 1 MHz to
1.25 GHz with guaranteed low additive jitter, low skew, and low propagation delay
variability. The Si53315 features minimal cross-talk and provides superior supply
noise rejection, simplifying low jitter clock distribution in noisy environments.
Independent core and output bank supply pins provide integrated level translation
without the need for external circuitry.
Functional Block Diagram
Ordering Information:
See page 25.
Pin Assignments
Si53315
OE2 1
SFOUT[0] 2
OE1 3
Q2 4
Q2 5
GND 6
Q1 7
Q1 8
Q0 ⁹
Q0 ¹⁰
OE0 11
GND
PAD
33 OE7
32 SFOUT[1]
31 OE8
30 _Q7
29 Q7
28 NC
27 Q8
26 Q8
25 Q9
24 Q9
23 OE9
Patents pending
VREF
Vref
Generator
Power
Supply
Filtering
CLK0
CLK0
CLK1
CLK1
CLK_SEL
Switching
Logic
VDDOA
OE[0:4]
Q0, Q1, Q2, Q3, Q4
Q0, Q1, Q2, Q3, Q4
SFOUT[1:0]
VDDOB
OE[5:9]
Q5, Q6, Q7, Q8, Q9
Q5, Q6, Q7, Q8, Q9
Preliminary Rev. 0.4 10/12
Copyright © 2012 by Silicon Laboratories
Si53315
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.