ISL6398 Datasheet, PDF (55/57 Pages) Intersil Corporation – Programmable soft-start rate and DVID rate

ISL6398
Component Placement
Within the allotted implementation area, orient the switching
components first. The switching components are the most critical
because they carry large amounts of energy and tend to generate
high levels of noise. Switching component placement should take
into account power dissipation. Align the output inductors and
MOSFETs such that space between the components is minimized
while creating the PHASE plane. Place the Intersil MOSFET driver
IC as close as possible to the MOSFETs they control to reduce the
parasitic impedances due to trace length between critical driver
input and output signals. If possible, duplicate the same
placement of these components for each phase.
Next, place the input and output capacitors. Position the high
frequency ceramic input capacitors next to each upper MOSFET
drain. Place the bulk input capacitors as close to the upper
MOSFET drains as dictated by the component size and
dimensions. Long distances between input capacitors and
MOSFET drains result in too much trace inductance and a
reduction in capacitor performance. Locate the output capacitors
between the inductors and the load, while keeping ceramic
capacitors in close proximity to the microprocessor socket.
To improve the chance of first pass success, it is very important
to take time to follow the above outlined design guidelines and
Intersil generated layout check list, see more details in
“Voltage Regulator (VR) Design Materials” on page 55. Proper
planning for the layout is as important as designing the circuits.
Running things in a hurry, you could end up spending weeks and
months to debug a poorly-designed and improperly laid out
board.
Powering Up And Open-Loop Test
The ISL6398 features very easy debugging and powering up. For
first-time powering up, an open-loop test can be done by applying
sufficient voltage (current limiting to 0.25A) to V_CC, signal high to
TM_EN_OTP (>1.05V) and EN_PWR_CFP (>0.9V and less than
3.5V) pins with the input voltage (VIN) disconnected.
1. Each PWM output should operate at maximum duty cycle and
correct switching frequency.
2. Read data in DC and DD of PMBus to confirm its proper
setting.
3. If 5V drivers are used and share the same rail as V_CC, the
proper switching on UGATEs and LGATEs should be seen.
4. If 12V drivers are used and can be disconnected from VIN and
sourced by an external 12V supply, the proper switching on
UGATEs and LGATEs should be observed.
5. If the above is not properly operating, you should check
soldering joint, resistor register setting, Power Train
connection or damage, i.e, shorted gates, drain and source.
Sometimes the gate might measure short due to residual
gate charge. Therefore, a measured short gate with
ohmmeter cannot validate if the MOSFET is damaged unless
the Drain to Source is also measured short.
6. When re-work is needed for the L/DCR matching network, use
an ohmmeter across the C to see if the correct R value is
measured before powering the VR up; otherwise, the current
imbalance due to improper re-work could damage the power
trains.
7. After everything is checked, apply low input voltage (1-5V)
with appropriate current limiting (~0.5A). All phases should
be switching evenly when AUTO disabled.
8. Remove the pull-up from EN_PWR_CFP pin, using bench
power supplies, power-up V_CC with current limiting
(typically ~ 0.25A if 5V drivers included) and slowly increase
Input Voltage with current limiting. For typical application, V_CC
limited to 0.25A, VIN limited to 0.5A should be safe for
powering up with no load. High core-loss inductors likely need
to increase the input current limiting. All phases should be
switching evenly.
Voltage Regulator (VR) Design
Materials
To support VR design and layout, Intersil also developed a set of
worksheets and evaluation boards, as listed in Tables 20 and 21,
respectively. The tolerance band calculation (TOB) worksheets for
VR output regulation and IMON have been developed using the
Root Sum Squared (RSS) method with 3 sigma distribution point
of the related components and parameters. Note that the
“Electrical Specifications” table beginning on page 10 specifies
no less than 6 sigma distribution point, not suitable for RSS TOB
calculation. Contact Intersil’s local office or field support for the
latest available information.
TABLE 20. AVAILABLE DESIGN ASSISTANCE MATERIALS
ITEM
DESCRIPTION
0 Design and Validation
1 Design Worksheet for Compensation and Component
Selection
2 SMBus/PMBus/I²C Communication Tool with Software
3 Resistor Register Calculator
4 Layout Design Guidelines
5 Evaluation Board Schematics in OrCAD Format and Layout in
Allegro Format
NOTE: For worksheets, please contact Intersil Application support
at www.intersil.com/design/.
EVALUATION BOARDS
ISL6398EVAL1Z
ISL6398EVAL2Z
PACKAGE
5x5 40Ld
5x5 40Ld
TABLE 21. AVAILABLE EVALUATION BOARDS
TARGETED APPLICATIONS
SMBus/PMBus/I²C
3-Phase POL with ISL99140, 6x6 DrMOS
Yes
Digital Compensation with NVM
6-Phase with ISL99140, 6x6 DrMOS
Yes
Digital Compensation with NVM
PEAK EFFICIENCY ICCMAX (A)
93%, 1.2V@40A 100A
94%, 1.8V@50A 215A
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August 13, 2015