ISL6398 Datasheet, PDF (24/57 Pages) Intersil Corporation – Programmable soft-start rate and DVID rate

ISL6398
The regulated output voltage is reduced by the droop voltage
V_DROOP. The output voltage as a function of load current is
derived by combining Equation 10 with the appropriate sample
current expression defined by the current sense method
employed, as shown in Equation 11:
V_OUT
=
V_REF
–



I--_{L----O-N---A----D--}
R-----_I^R--_S^---X-_E^----_N^--
R _{F B}
(EQ. 11)
where V_REF is the reference voltage (DAC), I_LOAD is the total
output current of the converter, R_ISEN is the sense resistor
connected to the ISEN+ pin, and R_FB is the feedback resistor, N is
the active channel number, and R_X is the DCR, or R_SENSE
depending on the sensing method.
Therefore, the equivalent loadline impedance, i.e. Droop
impedance, is equal to Equation 12:
R_LL = --R---N-^F----^B-- _R-----I^R--_S---^X-_E----_N--
(EQ. 12)
The major regulation error comes from the current sensing
elements. To improve load-line regulation accuracy, a tight DCR
tolerance of inductor or a precision sensing resistor should be
considered.
In addition, the overall load-line can be programmed to fit the
application needed by the PMBus registers: B0h[7:0] for
Load-Line and E4h[9:5] for DC offset. Curve 3 shown in Figure 13,
makes a steeper load line than the target to fully utilize the total
tolerance band, reduce the output capacitor count and cost.
OFFSET = R1* {I(E4h[9:5])-* I(E4h[4:0])}*D3[0]
2
1
VOUT_MAX
4
3
VOUT_MIN
OFFSET + LLTARGET
R1 = LLTARGET
OFFSET + (> LLTARGET)
R1 > LLTARGET
LOAD (A)
FIGURE 13. PROGRAMMABLE LOAD-LINE REGULATION
Dynamic VID
Some applications need to make changes to their voltage as part
of normal operation. They direct the core-voltage regulator to do
this by making changes to the VID during regulator operation.
The power management solution is required to monitor the DAC
and respond to on-the-fly VID changes in a controlled manner.
Supervising the safe output voltage transition within the DAC
range of the load without discontinuity or disruption is a
necessary function of the voltage regulator.
Sixteen different slew rates can be selected for soft-start and
during Dynamic VID (DVID) transition for VR.
DVID
F6h[4:0]
0h
1h
2h
3h
4h
5h
6h
7h
TABLE 5. SLEW RATE OPTIONS
DVID SLEW RATE
(MINIMUM RATE)
(mV/µs)
DVID
F6h[4:0]
DVID SLEW RATE
(MINIMUM RATE)
(mV/µs)
0.315
8h
4.0
0.625
9h
4.44
1.25
Ah
5.0
2.5
Bh
5.6
2.85
Ch
6.66
3.07
Dh
8.0
3.33
Eh
10
3.63
Fh
13.25
During dynamic VID transition and VID step up, the overcurrent
trip point increases by 140% to avoid falsely triggering OCP
circuits, while the overvoltage trip point will follow the DAC+OVP
level, programmable via PMBus (D8h[2:0]).
Operation Initialization
Prior to converter initialization, proper conditions must exist on
the enable inputs and V_CC. When the conditions are met, the
controller begins soft-start. Once the output voltage is within the
proper window of operation, VR_RDY asserts logic high.
Enable and Disable
While in shutdown mode, the PWM outputs are held in a
high-impedance state (or pulled to 40% of V_CC) to assure the
drivers remain off. The following input conditions must be met
before the ISL6398 is released from shutdown mode.
1. The bias voltage applied at V_CC must reach the internal
power-on reset (POR) rising threshold. Once this threshold is
reached, proper operation of all aspects of the ISL6398 is
guaranteed. Hysteresis between the rising and falling
thresholds assure that once enabled, ISL6398 will not
inadvertently turn off unless the bias voltage drops
substantially (see “Electrical Specifications” on page 10).
2. The ISL6398 features an enable input (EN_PWR_CFP) for
power sequencing between the controller bias voltage and
another voltage rail. The enable comparator holds the
ISL6398 in shutdown until the voltage at EN_PWR_CFP rises
above 0.85V. The enable comparator has about 100mV of
hysteresis to prevent bounce. It is important that the drivers
reach their POR level before the ISL6398 becomes enabled.
The schematic in Figure 14 demonstrates sequencing the
ISL6398 with ISL99140 DrMOS and the ISL66xx family of
Intersil MOSFET drivers.
3. The voltage on TM_EN_OTP must be higher than 1.08V
(typically) to enable the controller. This pin is typically
connected to the output of VTT VR. However, since the
TM_EN_OTP pin is also used for thermal monitoring, it will
assert SM_PMALERT# pin low due to thermal alert prior to
start-up, therefore, it needs to use CLEAR_FAULT (03h)
command to clear the SM_PMALERT# pin and
STATUS_BYTE (78h) after power-up. There is no effect on
normal operation if SM_PMALERT# and STATUS_BYTE are not
used.
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FN8575.1
August 13, 2015