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ISL6398 Datasheet, PDF (41/57 Pages) Intersil Corporation – Programmable soft-start rate and DVID rate
ISL6398
COMMAND
CODE
DFh[8:0]
ACCESS
R/W
E1h[6:0] R/W
E2[11:0] R/W
TABLE 14. SMBus, PMBus, AND I2C WRITE AND READ REGISTERS
WRITE
PROTECT
LEVEL
DEFAULT
COMMAND NAME
DESCRIPTION
10h NVM_BANK
PROTECTION_DISABLE
[UV_WARN, OV_WARN,OTP, UVP, IPH_LIMIT, OCP_V, OCP_I,
IIN_OCP, OVP]; OCP_V = IMON_3V Trip; OCP_I = 100uA trip;
IIN_OCP = input OCP; OVP = Output overvoltage trip;
IPH_LIMIT = Phase Current Limiting; UVP = Undervoltage
Protection; OTP = TMAX Trip; OV_WARN = Overvoltage
Warning; UV_WARN = Undervoltage warning.
10h NVM_BANK
SET_UVP_DLY_ACTION
Bit[3:0] - Output Under-voltage Protection Level:
0h = 105mV, 1h = 141mV; 2h = 178mV; 3h = 214mV;
4h = 252mV; 5h = 291mV; 6h = 328V; 7h = 402mV;
UVP = DAC - UVP Level with 19mV hysteresis;
UVP_WARNING = DAC-UVP+66mV (or higher) with 17mV
Hysteresis (see Electrical Specification on Page 10 for more
details). UVP and UVP Warning can be disabled via DFh.
Bit[5:4]: Output Under-voltage Protection delay:
0h = 10µs, 1h = 20µs, 2h= 40µs, 3h = 120µs
Bit[6] - UVP_Actions:
0h= Monitor Only; 1h = Hiccup (same as OCP timing)
10h NVM_BANK ADVANCED_PSCOMP_CONFIG Bit[2:0] PS2 to PS1/0 DCM OFFSET, but make PS0/1 to 2
transition worse, which can help with Bit[8:6]. C2_pop1
momentarily offsets it back up so no dip if C2_pop1 > = bit[2:0]
(NOT USED).
0h = 0mV, 1h = 20mV…….7h = 140mV.
Bit[4:3]: High-Frequency Transient VCOMP Bottom Clamp; the
lower the better.
0h = 20mV, 1h = 40mV, 2h = 60mV, 3h = 80mV
Bit[5] - DECAY_COMP_OFFSET, higher is better (NOT USED))
0h = 100mV, 1h = 200mV
Bit[8:6] - PS0/1 to PS2 Offset (C2_pop1), This likely will take the
same value as Bit[2:0] or higher. This improve PS0/1 to PS2
transition, no affect on PS2 to PS1/0.
0h = 0mV, 1h = 20mV…….7h = 140mV
Bit[10:9] PS1 to PS0 Offset (C2_pop2), no affect on other
transitions.
0h = 0, 1h = 20mv, 2h = 40mV, 3h = 60mV
NOTE:
PS2: Diode Emulation (DE) Operation (Not used)
PS1: 1-Phase or 2-Phase Operation in Auto Based Upon NPSI
PS0: > NSPI Operation Phase
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FN8575.1
August 13, 2015