ISL6398 Datasheet, PDF (31/57 Pages) Intersil Corporation – Programmable soft-start rate and DVID rate

ISL6398
ceramic capacitors and the inductor, yielding oscillation or audio
noise during audio frequency range of heavy load transient. In
addition, since Z_NTC network steals portion of sensed current
from R_IN1, input current reading will have offset.
In many cases, a narrow input-rail PCB trace (but wide enough to
carry DC current) is sufficient to serve as the isolation path. Thus,
the input current sensing can simply be realized with a dedicated
power resistor, as shown in Figure 28.
LIN
DCR
50nH
0.3m 
VIN
VIN_HS_MOSFET
165 R_IN1
ZNTC
Rsn
215
NTC
2k
Rpn
10.2k
PLACE NTC
CLOSE TO
LIN
402RIN2
ISENIN-
(PIN 1)
1.8µF
10nF
0.1µF
ISENIN+
(PIN 2)
PLACE CLOSE
TO THE
CONTROLLER
FIGURE 27. INPUT DCR-SENSING CONFIGURATION
The full scale of input current sensing is 10µA, read 1Fh with
READ_IIN(89h), via PMBus, while the input over-current trip point
is at 15µA (Programmable via F6[6:5]). A greater than 40µs time
constant [C*R_IN1*R_IN2)/(R_IN1+R_IN2)] might be needed if the
average input current reporting is preferred; and it also reduces
chance to trigger CFP during heavy load transient depending
upon the input filter. A design worksheet to select these
components is available for use. Please contact Intersil
Application support at www.intersil.com/design.
VIN
43.2 R IN1
562 R_IN2
RSENIN
0.3m
LR_SENIN
1nH
0.1µF C
10nF
VIN_HS_MOSFET
0.1µF
PLACE CLOSE
TO THE
CONTROLLER
ISENIN-
(PIN 1)
ISENIN+
(PIN 2)
FIGURE 28. INPUT R-SENSING CONFIGURATION
1.5M
499k
VIN_HS_MOSFET
PLACE CLOSE
TO THE
CONTROLLER
0.1µF
ISENIN-
(PIN 1)
ISENIN+
(PIN 2)
FIGURE 29. DISABLE PIN AND IIN CONFIGURATION
Auto-phase Shedding
The ISL6398 incorporates auto-phase shedding feature to
improve light to medium load range. The phase current dropping
threshold is programmable with the resistor on auto pin. The
efficiency-optimized current trip point (I1) from 1-Phase to
2-Phase operation is approximated with Equation 28, which is kx
larger than the efficiency-optimized current trip step
(dI = I3 - I2) in between from 2-phase to 3-phase (I2) and from
3-phase to 4-phase (I3). The optimized-efficiency current trip
point difference between phases remain constant I1/k, as
expressed in Equation 29 and Figure 30
I1  _E--²---_S--^--_R-^--^P--_I--_NQ-----^G_---_D---+---+-^P----_R-^C---_O-^O----_NR-----^E_+-----+L----_D^P----_S-^C----^O_---_F-^S---_S-^S---_W-^--
(EQ. 28)
R_ON = D  r_{DSON_UP} + 1 – D  r_{DSON_LOW} + DCR
where P_QG is the per-phase gate charge loss, P_CORE is the
inductor core loss, P_QOSS is the sum of high-side and low-side
MOSFETs’ output charge loss.
I3 ^{I4 I5}
I2
I1
When not used, connect ISENIN+ to VIN and a resistor divider
with a ratio of 1/3 on ISENIN± pin, say 499k Ohm in between
ISENIN± pins and then 1.5MΩ from ISENIN- to ground
(see Figure 29).
LOAD (A)
FIGURE 30. EFFICIENCY VS. PHASE NUMBER
I_{IMON_OPTIMIZED_1_PHASE}  _N-⁶----⁴_M-----^_A--^D--_X---^C--_---_RR----_S--^--_E-^I--¹-_T--
R_AUTO = -_I-_I--_M-----_O----_N-----_{_}---_O----_P---_T---_I-¹-_M--^.--²_I--_Z--^V-_E---_D----_{_}---₁---_{_}---_P---_H----_A----_S---_E--
(EQ. 29)
(EQ. 30)
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FN8575.1
August 13, 2015