ISL6398 Datasheet, PDF (33/57 Pages) Intersil Corporation – Programmable soft-start rate and DVID rate

ISL6398
TABLE 9. PMBus (DC) RESISTOR READER EXAMPLE
PMBus (DC)
R_UP
(kΩ
R_DW
PMBus
RECOMMENDED
(kΩ 8-Bit ADDRESS APPLICATIONS
00h
OPEN 10
80
10mV/Step
01h
49.9 12.4
82
10mV/Step
02h
45.3 12.7
84
10mV/Step
03h
43.2 13.3
86
10mV/Step
08h
29.4 15
C0
10mV/Step
09h
28 15.4
C2
10mV/Step
0Ch
24.3 17.4
C8
10mV/Step
0Dh
23.2 17.8
CA
10mV/Step
10h
20 19.6
E0
10mV/Step
11h
19.6 20.5
E2
10mV/Step
14h
17.4 23.2
E8
10mV/Step
15h
16.9 24.3
EA
10mV/Step
80h
OPEN 499
80
5mV/Step
81h
374 93.1
82
5mV/Step
82h
340 95.3
84
5mV/Step
83h
316 100
86
5mV/Step
88h
221 113
C0
5mV/Step
89h
210 115
C2
5mV/Step
8Ch
182 130
C8
5mV/Step
8Dh
174 133
CA
5mV/Step
90h
150 147
E0
5mV/Step
91h
147 154
E2
5mV/Step
94h
130 174
E8
5mV/Step
95h
127 182
EA
5mV/Step
TABLE 10. PMBus (DD) RESISTOR READER EXAMPLE
R_UP R_DW
PMBus (DD) (kΩ (kΩ
NVM
BT
00h
OPEN 10
NVM0
NVM_BT
20h
118 26.1
NVM1
NVM_BT
40h
196 43.2
NVM2
NVM_BT
60h
294 64.9
NVM3
NVM_BT
80h
422 93.1
NVM4
NVM_BT
A0h
590 130
NVM5
NVM_BT
C0h
825 182
NVM6
NVM_BT
E0h
OPEN 499
NVM7
NVM_BT
01h
49.9 12.4
NVM0
0.0V
10h
20 19.6
NVM0
1.7V, 10mV/Step
09h
28 15.4
NVM0
0.6V, 5mV/Step
1.2V, 10mV/Step
TABLE 10. PMBus (DD) RESISTOR READER EXAMPLE (Continued)
R_UP R_DW
PMBus (DD) (kΩ (kΩ
NVM
BT
32h
40.2 45.3
NVM1
0.9V, 5mV/Step
1.8V, 10mV/Step
55h
59 84.5
NVM2
1.0V, 5mV/Step
2.0V, 10mV/Step
79h
78.7 163
NVM3
1.2V, 5mV/Step
2.4V, 10mV/Step
9Fh
95.3 367
NVM4
1.5V, 5mV/Step
2.0V, 10mV/Step
B2h
196 226
NVM5
1.8V, 10mV/Step
DAh
215 475
NVM6
2.5V, 10mV/Step
NOTE: More options in resistor reader calculator. NVM_BT = Boot Voltage
Loaded from the Bank, not fixed by resistor reader.
Memory Banks
The ISL6398 has 8 memory banks to store up
(STORE_USER_ALL, 15h) to 8 different configurations, selectable
via PMBus (DEh) or resistor to GND on the NVM_BANK pin, as in
Table 11. No decoupling capacitor is allowed on the pin. Prior to
the soft-start, the selection of memory bank is stored in the data
registers of PMBus (DDh). They are reset by V_CC POR. In addition,
the selected memory bank can be overridden by PMBus (DEh).
Only the selected memory bank’s configuration is loaded
(RESTORE_USER_ALL,16h) into the operating memory to have
control on the VR system prior to issuing soft-start.
TABLE 11. MEMORY BANK (PMBus, DD)
DEh
MEMORY BANK NAME
00h
USER_NVM0
01h
USER_NVM1
02h
USER_NVM2
03h
USER_NVM3
04h
USER_NVM4
05h
USER_NVM5
06h
USER_NVM6
07h
USER_NVM7
Other than device’s PMBus Addresses and VR operation mode,
all system design parameters are programmed by PMBus, as
summarized in Table 12 and detailed in Table 14.
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August 13, 2015