ISL6398 Datasheet, PDF (30/57 Pages) Intersil Corporation – Programmable soft-start rate and DVID rate

ISL6398
T_COMP = T_CSC – T_NTC
(EQ. 23)
6. Run the actual board under full load again with the proper
resistors connected to the “TCOMP” pin.
7. Record the output voltage as V1 immediately after the output
voltage is stable with the full load. Record the output voltage
as V2 after the VR reaches the thermal steady state.
8. If the output voltage increases over 3mV as the temperature
increases, i.e. V2 - V1 > 3mV, reduce “TCOMP” value; if the
output voltage decreases over 3mV as the temperature
increases, i.e. V1 - V2 > 3mV, increase “TCOMP” values.
Dynamic VID Compensation (DVC)
During DVID transitions, extra current builds up in the output
capacitors due to the C*dv/dt. The current is sensed by the
controller and fed across the feedback resistor creating extra
droop (if enabled) and causing the output voltage not properly
tracking the DAC voltage. An independent compensation for
DVID up and DVID down are implemented to optimize the DVID
transition (Patent Pending), programmable by D7 and D9,
respectively.
Programmable Compensation
The ISL6398 controller utilizes Intersil’s proprietary Advanced Linear
EAPP Digital control scheme that is the best modulation scheme in
the industry to achieve linear response for both transient and
current balance and can process voltage and current information in
real time for fast control and high speed protection and realize
digital power management capability and flexibility and. The digital
compensation covers a wide range of poles and zeros, as in
Figure 25, suitable for computing, networking, ASIC, and many
general purpose applications. Refer ISL6398 GUI on Table 16 for
more details and advanced features.
FIGURE 25. TYPE III Compensation Poles and Zero Range
Catastrophic Fault Protection
A catastrophic failure is a failure that will result in an exothermic
event if the power source is not removed. A predominate
catastrophic failure is a high-side FET shorting, which can cause
either output overvoltage or input overcurrent event. When the
ISL6398 detects either event, an internal switch is turned on to pull
the EN_PWR_CFP pin to V_CC, as an indication of a component
failure in the regulator’s power train. As shown in Figure 26, a CFP
fault signal can be generated by using a resistor divider on this pin.
To be able to apply the signal to the PS_ON# switch of an ATX power
supply or a simply external switch (2N7002), the CFP fault signal
should be lower than 0.8V at maximum input voltage, V_IN(max) and
higher than 3V at lowest normal operational V_CC (4.5V) when the
input voltage (VIN) is removed. Given such conditions, the equivalent
(in parallel) impedance of the upper leg (R_UP) and lower leg
(R_DW = R_DW1 + R_DW1) should be higher than 1k. For instance, if
we select the total lower leg impedance (R_DW) as 9.39k, then the
R_UP is calculated as in Equation 25, 100k for a maximum POR of
10.72V, The lower leg impedance is then calculated by 2.74k and
6.65k, as in Equations 26 and 27, respectively.
R_DW = R_DW1 + R_DW2
(EQ. 24)
R_UP = ^{V-----I--N-----}--P-----O-----R--0--^--.-9m----2--a-V---x---^---^–-----0---.--9---2----V--  R_DW
R_DW1 = -V----I--N-0----.^-8-m---V---a----x---^  R_UP + R_DW
R_DW2 = R_DW – R_DW1
(EQ. 25)
(EQ. 26)
(EQ. 27)
VIN
VCC
RUP
CFP
RDW1
RDW2
EN_PWR_CFP
CFP
EN_PWR
RESET
ISL6375, ISL6376
FIGURE 26. BI-DIRECTIONAL EN_PWR_CFP
Prior to an exothermic event, the fault signal (CFP) should be used
on the platform to remove the power source either by firing a
shunting SCR to blow a fuse or by turning off the AC power supply.
Input Current Sensing
The input current sensing uses Intersil patented technique to
overcome the high common-mode input requirement challenge.
An R-C network with thermal compensation across the inductor
(LIN) extracts the DCR voltage, as shown in Figure 27, while the C
might need to be split into 2, one close the LIN and one close to
the controller. The input inductor can be used for current sensing
and has benefit of isolating noise from the rest of the board.
However, when there are insufficient bulk capacitors on the
power-stage side, a resonant tank can be formed by input
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FN8575.1
August 13, 2015