ISL6398 Datasheet, PDF (44/57 Pages) Intersil Corporation – Programmable soft-start rate and DVID rate

ISL6398
TABLE 14. SMBus, PMBus, AND I²C WRITE AND READ REGISTERS
COMMAND
CODE
ACCESS
WRITE
PROTECT
LEVEL
DEFAULT
COMMAND NAME
DESCRIPTION
F4[5:0]
R/W
10h NVM_BANK
OCP_ICL_TRIM
Bit [3:0]- OCP Level (IOCP_AVG and ICL):
0h = 1.0, 1h = 1.1, 2h = 1.2; 3h = 1.4, 4h = 1.5, 5h = 1.6 of IMON
Bit [5:4]- Output Current Cycle Limiting (ICL):
0h = 125%, 01h = 110%, 2h = 100%; 3h = 95%, 4h = 0%,
5h = 85%, 6h = 80%, 7h = 70%
F5h[6:0] R/W
10h NVM_BANK
SET_FREQ
0h- 7Fh = 120kHz to 2025kHz, 15kHz/Step
F6h[6:0] R/W
10h NVM_BANK
DVID_CFP
Bit[4:0] - Soft-Start and DVID Rate
0h = 0.315mV/µs; 1h = 0.625mV/µs; 2h = 1.25mV/µs;
3h = 2.5mV/µs; 4h = 2.85mV/µs; 5h = 3.07mV/µs;
6h = 3.33mV/µs; 7h = 3.63mV/µs, 8h = 4.0mV/µs,
9h = 4.44 mV/µs; Ah = 5.0mV/µs; Bh = 5.6mV/µs;
Ch = 6.66mV/µs; Dh = 8.0mV/µs; Eh = 10mV/µs;
Fh = 13.25mV/µs
Bit[6:5] - IN_OCP
0h = 100%, 1h = 110%, 2h = 120%,3h = 130%
F7h[2:0]
F8h[2:0]
F9h[2:0]
FAh[2:0]
FBh[2:0]
FCh[2:0]
R/W
10h NVM_BANK
F7 = BAL_TRIM_PHASE1
F8 = BAL_TRIM_PHASE2
F9 = BAL_TRIM_PHASE3
FA = BAL_TRIM_PHASE4
FB = BAL_TRIM_PHASE5
FC = BAL_TRIM_PHASE6
0h = -12% of full scale
1h = -9% of full scale
2h = -6% of full scale
3h = -3% of full scale
4h = No Offset
5h = +3% of full scale
6h = +6% of full scale
7h = +9% of full scale
FD[15:0]
R
N/A
CHECK_SUM
Read Calculated CheckSum for individual NVM Bank checksum
10ms after execute EEh(80h) command and 60ms for the total
checkSum after execute EEh(40h).
03h
W
40h
CLEAR_FAULTS
Clear “Latched” Fault Registers in 78h For Selected Rail
ARA
R
ALERT_RESPONSE_ADDRESS 8-bit Address: 0001_1001, 19h; 7-bit Address: 0C
COMPENSATION REGISTERS
B0h[7:0] R/W
00h NVM_BANK
R₁
250 Steps: 1.01018x
00h = 599.0
01h = 605.1
...
F9h = 7471
B1h[4:0] R/W
00h NVM_BANK
R2
30 Steps: 1.1x
00h = 2k
01h = 2.2
...
1Dh = 32K
B2h[4:0]
B3h[4:0]
B4h[4:0]
B5h[4:0]
B6h[4:0]
B7h[4:0]
R/W
R/W
R/W
R/W
R/W
R/W
00h NVM_BANK
00h NVM_BANK
00h NVM_BANK
00h NVM_BANK
00h NVM_BANK
00h NVM_BANK
R3_6PHASE
R3_5PHASE
R3_4PHASE
R3_3PHASE
R3_2PHASE
R3_1PHASE
30 Steps: 1.1x
00h = 50k
01h= 55
...
1Dh =790
B2 = 1Fh, will Remove R3/C3 for all Phase Count.
Larger R3 and/or smaller C3 help reduce output noise coupling.
Recommend to keep R3/C3 the same values for highest phase
count (Nmax) and Nmax-1 Phase count for smoother transition.
B8h[5:0] R/W
00h NVM_BANK
C1
42 Steps: 1.1x
00h = 10pF
01h = 11pF
...
29h = 500pF
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August 13, 2015