HYB5116400BJ-50-60 Datasheet, PDF (9/26 Pages) Siemens Semiconductor Group – 4M x 4-Bit Dynamic RAM 2k & 4k Refresh

HYB 5116(7)400BJ-50/-60
HYB 3116(7)400BJ/BT-50/-60
4M × 4 DRAM
AC Characteristics (cont’d) ^{5, 6}
T_A = 0 to 70 °C, V_CC = 5 V ± 10 % / V_CC = 3.3 V ± 0.3 V, t_T = 5 ns
Parameter
Symbol
Limit Values
Unit Note
-50
-60
min. max. min. max.
OE access time
t_OEA
Column address to RAS lead time
t_RAL
Read command setup time
t_RCS
Read command hold time
t_RCH
Read command hold time referenced to RAS t_RRH
CAS to output in low-Z
t_CLZ
Output buffer turn-off delay
t_OFF
Output buffer turn-off delay from OE
t_OEZ
Data to OE low delay
t_DZO
CAS high to data delay
t_CDD
OE high to data delay
t_ODD
– 13 – 15 ns
25 – 30 – ns
0 – 0 – ns
0
–
0
–
ns ¹¹
0
–
0
–
ns ¹¹
0
–
0
–
ns ⁸
0
13 0
15 ns ¹²
0
13 0
15 ns ¹²
0
–
0
–
ns ¹³
13 –
15 –
ns ¹⁴
13 –
15 –
ns ¹⁴
Write Cycle
Write command hold time
Write command pulse width
Write command setup time
Write command to RAS lead time
Write command to CAS lead time
Data setup time
Data hold time
Data to CAS low delay
t_WCH
t_WP
t_WCS
t_RWL
t_CWL
t_DS
t_DH
t_DZC
8–
8–
0–
13 –
13 –
0–
10 –
0–
10 –
10 –
0–
15 –
15 –
0–
10 –
0–
ns
ns
ns ¹⁵
ns
ns
ns ¹⁶
ns ¹⁶
ns ¹³
Read-Modify-Write Cycle
Read-write cycle time
RAS to WE delay time
CAS to WE delay time
Column address to WE delay time
OE command hold time
t_RWC
t_RWD
t_CWD
t_AWD
t_OEH
126 –
68 –
31 –
43 –
13 –
150 –
80 –
35 –
50 –
15 –
ns
ns ¹⁵
ns ¹⁵
ns ¹⁵
ns
Semiconductor Group
9
1998-10-01