HYB5116400BJ-50-60 Datasheet, PDF (7/26 Pages) Siemens Semiconductor Group – 4M x 4-Bit Dynamic RAM 2k & 4k Refresh

HYB 5116(7)400BJ-50/-60
HYB 3116(7)400BJ/BT-50/-60
4M × 4 DRAM
DC Characteristics (cont’d)
T_A = 0 to 70 °C, V_SS = 0 V, t_T = 2 ns
Parameter
Symbol Limit Values Unit Notes
min. max.
2k 4k
Common Parameters
Input leakage current
I_I(L)
(0 V ≤ V_IH ≤ V_CC + 0.3 V, all other pins = 0 V)
Output leakage current
I_O(L)
(DO is disabled, 0 V ≤ V_OUT ≤ V_CC + 0.3 V)
Average V_CC supply current
I_CC1
-50 ns version
-60 ns version
(RAS, CAS, address cycling: t_RC = t_{RC MIN.})
Standby V_CC supply current (RAS = CAS = V_IH)
I_CC2
Average V_CC supply current, during RAS-only refresh I_CC3
cycles
-50 ns version
-60 ns version
(RAS cycling, CAS = V_IH, t_RC = t_{RC MIN.})
Average V_CC supply current,during fast page mode I_CC4
-50 ns version
-60 ns version
(RAS = V_IL, CAS, address cycling: t_PC = t_{PC MIN.})
Standby V_CC supply current
I_CC5
(RAS = CAS = V_CC – 0.2 V)
Average V_CC supply current, during CAS-before-RAS I_CC6
refresh mode
-50 ns version
-60 ns version
(RAS, CAS cycling: t_RC = t_{RC MIN.})
– 10 10 µA ¹
– 10 10 µA ¹
– 80 50 mA ^{2, 3, 4}
– 70 40 mA ^{2, 3, 4}
–
2 mA –
– 80 50 mA ^{2, 4}
– 70 40 mA ^{2, 4}
–
25
mA ^{2, 3, 4}
–
20
mA ^{2, 3, 4}
–
1 mA ¹
– 80 50 mA ^{2, 4}
– 70 40 mA ^{2, 4}
Semiconductor Group
7
1998-10-01