HYB5116400BJ-50-60 Datasheet, PDF (23/26 Pages) Siemens Semiconductor Group – 4M x 4-Bit Dynamic RAM 2k & 4k Refresh

HYB 5116(7)400BJ-50/-60
HYB 3116(7)400BJ/BT-50/-60
4M × 4 DRAM
Read Cycle
V_IH
RAS
V_IL
V_IH
CAS
V_IL
V_IH
Address
V_IL
V_IH
WE
V_IL
V_IH
OE
V_IL
I/O
V_IH
(Inputs) _VIL
I/O
V_OH
(Outputs) _VOL
Write Cycle
V_IH
WE
V_IL
V_IH
OE
V_IL
I/O
V_IH
(Inputs) _VIL
I/O
V_OH
(Outputs) _VOL
t _CSR
t _CHR
t _WRP
t _WRH
t _WRP
t _WRH
"H" or "L"
t _RAS
t _RP
t _RSH
t _CP
t _CAS
t _ASC
t _RAL
t _CAH
Column
t _AA
t _RCS
t _CAC
t _OEA
t _ASR
Row
t _RRH
t _RCH
t _DZC
t _DZO
t _CLZ
t _WCS
t _RWL
t _CWL
t _WCH
t _ODD
t _CDD
t _OFF
t _OEZ
Data OUT
t _DH
t _DS
Data IN
Hi Z
SPT03036
CAS-before-RAS Refresh Counter Test Cycle
Semiconductor Group
23
1998-10-01