HYB5116405BJ-50- Datasheet, PDF (8/28 Pages) Siemens Semiconductor Group – 4M x 4-Bit Dynamic RAM 2k & 4k Refresh

HYB 5116(7)405BJ-50/-60
HYB 3116(7)405BJ/BT(L)-50/-60
4M × 4 EDO-DRAM
Capacitance
T_A = 0 to 70 °C, f = 1 MHz
Parameter
Input capacitance (A0 to A11)
Input capacitance (RAS, CAS, WE, OE)
I/O capacitance (I/O1 to I/O4)
Symbol
C_I1
C_I2
C_IO
Limit Values
min.
max.
–
5
–
7
–
7
Unit
pF
pF
pF
AC Characteristics ^{5, 6}
T_A = 0 to 70 °C, V_CC = 5 V ± 10 % / V_CC = 3.3 V ± 0.3 V, t_T = 2 ns
Parameter
Symbol
Limit Values
Unit Note
-50
-60
min. max. min. max.
Common Parameters
Random read or write cycle time
RAS precharge time
RAS pulse width
CAS pulse width
Row address setup time
Row address hold time
Column address setup time
Column address hold time
RAS to CAS delay time
RAS to column address delay
RAS hold time
CAS hold time
CAS to RAS precharge time
Transition time (rise and fall)
Refresh period for 2k-refresh version
Refresh period for 4k-refresh version
Refresh period for Low Power Version
Read Cycle
Access time from RAS
Access time from CAS
t_RC
84 –
104 –
ns
t_RP
30 –
40 –
ns
t_RAS
50 10k 60 10k ns
t_CAS
8
10k 10 10k ns
t_ASR
0
–
0
–
ns
t_RAH
8
–
10 –
ns
t_ASC
0
–
0
–
ns
t_CAH
8
–
10 –
ns
t_RCD
12 37 14 45 ns
t_RAD
10 25 12 30 ns
t_RSH
13 –
15 –
ns
t_CSH
40 –
50 –
ns
t_CRP
5
–
5
–
ns
t_T
1
50 1
50 ns ⁷
t_REF
–
32 –
32 ms
t_REF
–
64 –
64 ms
t_REF
–
128 –
128 ms
t_RAC
–
50 –
60
ns ^{8, 9}
t_CAC
–
13 –
15
ns ^{8, 9}
Semiconductor Group
8
1998-10-01