HYB5116405BJ-50- Datasheet, PDF (7/28 Pages) Siemens Semiconductor Group – 4M x 4-Bit Dynamic RAM 2k & 4k Refresh

HYB 5116(7)405BJ-50/-60
HYB 3116(7)405BJ/BT(L)-50/-60
4M × 4 EDO-DRAM
DC Characteristics (cont’d)
T_A = 0 to 70 °C, V_SS = 0 V, t_T = 2 ns
Parameter
Symbol
Limit Values
min.
max.
2k 4k
Common Parameters
Input leakage current
I_I(L)
(0 V ≤ V_IH ≤ V_CC + 0.3 V, all other pins = 0 V)
Output leakage current
I_O(L)
(DO is disabled, 0 V ≤ V_OUT ≤ V_CC + 0.3 V)
Average V_CC supply current
I_CC1
-50 version
-60 version
(RAS, CAS, address cycling: t_RC = t_{RC MIN.})
Standby V_CC supply current
I_CC2
(RAS = CAS = V_IH)
Average V_CC supply current, during RAS-only I_CC3
refresh cycles
-50 version
-60 version
(RAS cycling, CAS = V_IH, t_RC = t_{RC MIN.})
Average V_CC supply current,during hyper page I_CC4
mode (EDO)
-50 version
-60 version
(RAS = V_IL, CAS, address cycling:
t_PC = t_{PC MIN.})
Standby V_CC supply current
I_CC5
(RAS = CAS = V_CC – 0.2 V)
Average V_CC supply current, during CAS-
I_CC6
before-RAS refresh mode
-50 version
-60 version
(RAS, CAS cycling: t_RC = t_{RC MIN.})
Average Self Refresh current
I_CC7
(CBR cycle with t_RAS > t_{RASS MIN.}, CAS held
low, WE = V_CC – 0.2 V, Address and
Din = V_CC – 0.2 V or 0.2 V)
– 10
10
– 10
10
–
80 50
–
70 40
–
2
–
80 50
–
70 40
–
35
–
30
–
1
200
–
80 50
–
70 40
–
250
Unit Notes
µA ¹
µA ¹
mA ^{2, 3, 4}
mA ^{2, 3, 4}
mA –
mA ^{2, 4}
mA ^{2, 4}
mA ^{2, 3, 4}
mA ^{2, 3, 4}
mA ¹
µA L-version
mA ^{2, 4}
mA ^{2, 4}
µA L-
version
only
Semiconductor Group
7
1998-10-01