HYB5116405BJ-50- Datasheet, PDF (12/28 Pages) Siemens Semiconductor Group – 4M x 4-Bit Dynamic RAM 2k & 4k Refresh

HYB 5116(7)405BJ-50/-60
HYB 3116(7)405BJ/BT(L)-50/-60
4M × 4 EDO-DRAM
Notes
1. All voltages are referenced to V_SS.
2. I_CC1, I_CC3, I_CC4 and I_CC6 depend on cycle rate.
3. I_CC1 and I_CC4 depend on output loading. Specified values are obtained with the output open.
4. Address can be changed once or less while RAS = V_IL. In case of I_CC4 it can be changed once
or less during a hyper page mode (EDO) cycle
5. An initial pause of 200 µs is required after power-up followed by 8 RAS cycles of which at least
one cycle has to be a refresh cycle, before proper device operation is achieved. In case of using
the internal refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of
8 RAS cycles are required.
6. AC measurements assume t_T = 2 ns.
7. V_{IH (MIN.)} and V_{IL (MAX.)} are reference levels for measuring timing of input signals. Transition times
are also measured between V_IH and V_IL.
8. Measured with the specified current load and 100 pF at V_OL = 0.8 V and V_OH = 2.0 V. Access
time is determined by the latter of t_RAC, t_CAC, t_AA, t_CPA, t_OEA . t_CAC is measured from tristate.
9. Operation within the t_{RCD (MAX.)} limit ensures that t_{RAC (MAX.)} can be met. t_{RCD (MAX.)} is specified as
a reference point only. If t_RCD is greater than the specified t_{RCD (MAX.)} limit, then access time is
controlled by t_CAC.
10.Operation within the t_{RAD (MAX.)} limit ensures that t_{RAC (MAX.)} can be met. t_{RAD (MAX.)} is specified as
a reference point only. If t_RAD is greater than the specified t_{RAD (MAX.)} limit, then access time is
controlled by t_AA.
11.Either t_RCH or t_RRH must be satisfied for a read cycle.
12.t_{OFF (MAX.)}, t_{OEZ (MAX.)} define the time at which the output achieves the open-circuit conditions and
are not referenced to output voltage levels. t_OFF is referenced from the rising edge of RAS or
CAS, whichever occurs last.
13.Either t_DZC or t_DZO must be satisfied.
14.Either t_CDD or t_ODD must be satisfied.
15.t_WCS, t_RWD, t_CWD and t_AWD are not restrictive operating parameters. They are included in the data
sheet as electrical characteristics only. If t_WCS > t_{WCS (MIN.)}, the cycle is an early write cycle and
data out pin will remain open-circuit (high impedance) through the entire cycle; if
t_RWD > t_{RWD (MIN.)}, t_CWD > t_{CWD (MIN.)} and t_AWD > t_{AWD (MIN.)}, the cycle is a read-write cycle and I/O will
contain data read from the selected cells. If neither of the above sets of conditions is satisfied, the
condition of I/O (at access time) is indeterminate.
16.These parameters are referenced to the CAS leading edge in early write cycles and to the WE
leading edge in read-write cycles.
17.When using Self Refresh mode, the following refresh operations must be performed to ensure
proper DRAM operation:
If row addresses are being refreshed on an evenly distributed manner over the refresh interval
using CBR refresh cycles, then only one CBR cycle must be performed immediately after exit
from Self Refresh.
If row addresses are being refreshed in any other manner (ROR - Distributed/Burst; or CBR-
Burst) over the refresh interval, then a full set of row refreshes must be performed immediately
before entry to and immediately after exit from Self Refresh.
Semiconductor Group
12
1998-10-01