HYB5116405BJ-50- Datasheet, PDF (10/28 Pages) Siemens Semiconductor Group – 4M x 4-Bit Dynamic RAM 2k & 4k Refresh

HYB 5116(7)405BJ-50/-60
HYB 3116(7)405BJ/BT(L)-50/-60
4M × 4 EDO-DRAM
AC Characteristics (cont’d) ^{5, 6}
T_A = 0 to 70 °C, V_CC = 5 V ± 10 % / V_CC = 3.3 V ± 0.3 V, t_T = 2 ns
Parameter
Symbol
Limit Values
Unit Note
-50
-60
min. max. min. max.
Hyper Page Mode (EDO) Cycle
Hyper page mode (EDO) cycle time
CAS precharge time
Access time from CAS precharge
Output data hold time
RAS pulse width in EDO mode
CAS precharge to RAS delay
OE setup time prior to CAS
t_HPC
20
t_CP
8
t_CPA
–
t_COH
5
t_RAS
50
t_RHCP
27
t_OES
5
Hyper Page Mode (EDO) Read-Modify-Write Cycle
Hyper page mode (EDO) read-write cycle t_PRWC 58
time
CAS precharge to WE
t_CPWD
41
CAS-before-RAS Refresh Cycle
CAS setup time
CAS hold time
RAS to CAS precharge time
Write to RAS precharge time
Write hold time referenced to RAS
t_CSR
10
t_CHR
10
t_RPC
5
t_WRP
10
t_WRH
10
CAS-before-RAS Counter Test Cycle
CAS precharge time (CAS-before-RAS
counter test cycle)
t_CPT
35
–
25
–
10
27 –
–
5
200k 60
–
32
–
5
–
68
–
49
–
10
–
10
–
5
–
10
–
10
–
40
–
ns
–
ns
32 ns ⁷
–
ns
200k ns
–
ns
–
ns
–
ns
–
ns
–
ns
–
ns
–
ns
–
ns
–
ns
–
ns
Self Refresh Cycle (L-Version only)
RAS pulse width
RAS precharge time
CAS hold time
t_RASS
t_RPS
t_CHS
100k –
95 –
– 50 –
100k –
110 –
– 50 –
ns ¹⁷
ns ¹⁷
ns ¹⁷
Semiconductor Group
10
1998-10-01