SDA9220-5 Datasheet, PDF (7/42 Pages) Siemens Semiconductor Group – Memory Sync Controller III

SDA 9220-5
3. Detailed Tables
Control 1 (subaddress 00)
Synchronization
External synchronization (line-locked)
Internal synchronization (free-running)
Blanking
Picture enabled
Picture blanked
MUX Invert, MUX Strobe
(Figure 9b shows the functional diagram of MUX)
MUX = L
MUX toggles with VS2 (for VS1 = H change to L)
MUX = H
MUX toggles with VS2 (for VS1 = H change to H)
VS Noise Reduction
Mode 1 (window)
Mode 2 (flywheel)
50/60-Hz-Standard
50-Hz standard
60-Hz standard
Deflection Raster
ααββ (with standard conversion)
αβ (w/o standard conversion)
αααα (with standard conversion)
αα (w/o standard conversion)
βαβα (with standard conversion)
not defined (w/o standard conversion)
Not defined
Semiconductor Group
123
Control Bit EXSYN (D7)
0
1
Control Bit BLK (D6)
0
1
Control Bit
MUXI (D5)
MUXS (D4)
0
0
0
1
1
0
1
1
Control Bit VNR (D3)
0
1
Control Bit Vert (D2)
0
1
Control Bit
VDM 1 (D1)
VDM 0 (D0)
0
0
0
1
1
0
1
1