SDA9220-5 Datasheet, PDF (29/42 Pages) Siemens Semiconductor Group – Memory Sync Controller III

a) Filter Circuitry
SDA 9220-5
b) Crystal Circuitry
Figure 10
Circuit Configuration for Filter and Crystal
Reset Behavior of SDA 9220-5
The circuitry has sensor logic for separately detecting values below the minimum supply level on the
V_DDA and the two V_DD pins. A reset cycle is initiated whenever such values are detected; the reset
time is preset by charging and discharging the pin capacitance of the reset input pin which is not
normally connected. This time can be extended by connecting RESI with an external capacitance.
The RESI pin can also be connected directly with a signal; a RES low level enables reset, a RES
high level terminates the reset. The internal circuit reset status is output via reset RESQ and can
then be used as an active low signal (low level = reset status). During the reset phase all the output
clocks generated by MSC (LL1.5X, LL3X, SCA and SCAD) are kept at low level. Upon completion
of the reset the SDA 9220-5 is in its basic (line-locked) mode. If no clock is applied to LLIN at this
point of time, the VCO in the PLL oscillates at its free-running frequency (5–20 MHz) and enables
all the output clocks derived from it.
– Typical Control Values for the Reset System
Initiation level for reset on V_DD
Low level on RESI
High level on RESI
Output low level on RESQ
Output high level on RESQ
V_DDR
V_RIL
V_RIH
< 3.9 V
< 1.5 V
> 2.3 V
V_QL ≤ 0.4 V (I_QL = 5 mA)
V_QH ≥ 2.4 V (I_QH = – 2.5 mA)
Semiconductor Group
145