SDA9220-5 Datasheet, PDF (21/42 Pages) Siemens Semiconductor Group – Memory Sync Controller III

SDA 9220-5
Pin Definitions and Functions (cont’d)
Pin No. Symbol
26
ADR
27
ZM
28
VS
29
VS1
30
MUX
31
LLSEL
32
CFH
33
OSCI
34
OSCQ
35
SCL
36
SDA
37
CSY
38
FRM
39
HS2
40
VS2
41
BLN2
42
BLN
43
LLIN
44
V_SS
Function
Description
Address select
Zoom signal
24_H for ADR = 0 or 26_H for ADR = 1
Control signal for Featurebox output interface IC:
supplies high level in zoom mode
Vertical sync
Input determines vertical position of TV picture for
50-or 60-Hz field frequency
Vertical sync
Output; noise suppressed
MUX switching
Switching signal for implementing simple frame
Featurebox
Select clock input A 27-MHz clock selected for LLSEL = low
Clock frequency
hold
For elimination of bottom flutter effect in VCR mode
Crystal oscillator
input
Crystal oscillator
output
Crystal clock as reference for recovery in tuner
scanning mode
Serial clock I²C Bus
Serial data I²C Bus
Composite sync
Horizontal and vertical sync pulses for Teletext
device in standard-conversion mode
Display frame signal Control signal output for possible insertion of colored
frame in multi-picture, picture-in still and still-in-
picture modes
Horizontal sync
display
Horizontal pulse for standard-converted picture
(31.25 / 31.47 kHz)
Vertical sync display Vertical sync pulse for data readout
Horizontal blank
display
Blanking signal for identifying active picture line for
data readout
Horizontal blank
Blanking signal input; high phase identifies active
picture line
Input clock
13.5 or 27 MHz
Digital ground
Semiconductor Group
137