SDA9220-5 Datasheet, PDF (25/42 Pages) Siemens Semiconductor Group – Memory Sync Controller III

SDA 9220-5
Characteristics (cont’d)
Parameter
Symbol
Limit Values
min. typ.
max.
Unit Test Condition
Output Clock SCA/Reference Clock: LL1.5X (refer to figure 9a)
H-pulse width
L-pulse width
Clock skew **⁾
Load capacitance
H-output voltage
L-output voltage
Period
t_WH
10
t_WL
10
t_SK
0
C_L
V_QH
2.4
V_QL
T_SCA1
34
37
25
ns
ns
15
ns
50
pF
V
0.4
V
40
ns
T_SCA2 ***⁾ 68
74
80
ns
T_SCA3 ***⁾ 136
148
160
ns
I_QH = – 2.5 mA
I_QL = 5 mA
Normal mode with
standard conversion
Normal mode without
standard conversion
or zoom mode with
standard conversion
Zoom mode without
standard conversion
Output Clock SCAD/Reference Clock: LL3X (refer to figure 9a)
Period
H-pulse width
L-pulse width
Clock skew *⁾
Load capacitance
H-output voltage
L-output voltage
T_SCAD
34
37
t_WH
12
t_WL
12
t_SK
– 15
C_L
V_QH
2.4
V_QL
40
ns
ns
ns
0
ns
50
pF
V
I_QH = – 2.5 mA
0.4
V
I_QL = 5 mA
*⁾ With steady-state PLL and provided that the capacitive load of the reference clock is identical or more.
**⁾ With steady-state PLL and provided that the capacitive load of the reference clock is identical or less.
***⁾ T_SCA2/3 are generated from T_SCA1 (by blanking the high phases).
Semiconductor Group
141