SDA9220-5 Datasheet, PDF (20/42 Pages) Siemens Semiconductor Group – Memory Sync Controller III

SDA 9220-5
Pin Definitions and Functions
Pin No. Symbol
1
V_SSA
2
V_DDA
3
RST
4
TE2
5
TE1
6
TE0
7
LL1.5X
8
NW
9
SCA
10
SCAD
11
LL3X
12
V_SS
13
V_DD
14
RE
15
RA
16
SAR
17
RB
18
SAC
19
WT
20
V_SS
21
WEI
22
DREQ
23
RESQ
24
RESI
25
V_DD
Function
Description
Analog ground
Analog supply
voltage
Positive supply voltage (+ 5 V) for analog part
PLL filter
Connecting pin for PLL filter
Test pin
Test pin
Test pin
27-MHz clock
Test pin; must be connected to V_SS for normal mode
Test pin; must be connected to V_SS for normal mode
Test pin; must be connected to V_SS for normal mode
27-MHz clock for devices of Featurebox generated
by PLL
Select standard
conversion
Standard-conversion switching; high level on this pin
means that standard conversion is activated
Serial clock
Serial clock for port A of TV-SAM
Serial address clock Serial address clock for TV-SAM
Clock
13.5-MHz clock for the devices of the Featurebox
generated by PLL
Digital ground
Digital supply
voltage
Positive supply voltage
Row enable
Control signal for TV-SAM
Read transfer
Via port A of TV-SAM
Serial row address For TV-SAM
Read transfer
Via port B of TV-SAM
Serial column
For TV-SAM
address and mode
Write transfer
Via port C of TV-SAM
Digital ground
Write inhibit
Write-enable input for direct disabling of write
operation for field memory
Data request
Data-request signal in 9-image mode for reduced
picture data; at same time I²C Bus sync signal for
picture processor
Reset output
Reset input
Digital supply
voltage
Normally on V_DD (active low)
Position supply voltage (+ 5 V) for digital part
Semiconductor Group
136