SDA9220-5 Datasheet, PDF (6/42 Pages) Siemens Semiconductor Group – Memory Sync Controller III

SDA 9220-5
2. Description
Slave Address:
0
0
1
0
0
1 ADR
Receiver Format:
S
Slave Address
0A
Sub Address
A
S: Start condition
A: Acknowledge
P: Stop condition
Data Byte
AP
Data Byte Formats:
Function Sub-
Data Byte
address _D7
D6
D5
D4
D3
D2
D1
D0
Control 1 00
EXSYN BLK MUXI MUXS VNR VERT VDM1 VDM0
Control 2 01
FLDM FLDC FLDF WDEL4 WDEL3 WDEL2 WDEL1 WDEL0
Control 3 02
STB FR
WM1 WM0 VPOS1 VPOS0 HPOS1 HPOS0
Zoom control 03
ZM
ZV2 ZV1 ZV0 ZH3 ZH2 ZH1 ZH0
HS2 phase 04
N864 HP6 HP5 HP4 HP3 HP2 HP1 HP0
FRM delay 05
FRDIS FRD6 FRD5 FRD4 FRD3 FRD2 FRD1 FRD0
CFH control 06
CFHW3 CFHW2 CFHW1 CFHW0 CFHP3 CFHP2 CFHP1 CFHP0
The subaddress is incremented automatically.
When the operating voltage is applied (power-up reset), all registers are set to 0.
Semiconductor Group
122