SDA9220-5 Datasheet, PDF (27/42 Pages) Siemens Semiconductor Group – Memory Sync Controller III

SDA 9220-5
Characteristics (cont’d)
Parameter
Symbol
Limit Values
min. typ.
max.
Unit Test Condition
Output Signals: SAR, SAC, RE/Reference Clock: SCAD (refer to figure 9b)
Delay time for SAR,
t_QD
SAC
Delay time for RE
Hold time
Load capacitance
H-output voltage
L-output voltage
t_QD
t_QH
6
C_L
V_QH
2.4
V_QL
25
ns
20
ns
ns
50
pF
V
I_QH = – 2.5 mA
0.4
V
I_QL = 5 mA
PLL-Filter Currents
Charge current
I_CH
Charge current
I_CH
Discharge current
I_DCH
Discharge current
I_DCH
80
70
– 80
– 70
Filter Elements (see figure 10a)
C_F1 ≈ 1.5 nF, R_F ≈ 1.8 kΩ, C_F2 ≈ 100 pF
250
250
– 300
– 300
µA V_QL = 1.9 V
µA V_QL = 2.9 V
µA V_QL = 1.9 V
µA V_QL = 2.9 V
Crystal (see figure 10b)
Nominal frequency
f_Q
Effect of temperature ∆f/f_Q
and accuracy of
adjustment
Temperature range
T_A
0
Load capacitance
C_L
Resonant impedance Z_R
Equivalent parallel C C_O
Crystal load
6.7500
MHz
33 ± 0.5
60
70
°C
pF
Ω
7 ± 20 % pF
0.1
mW
Semiconductor Group
143