SDA9220-5 Datasheet, PDF (11/42 Pages) Siemens Semiconductor Group – Memory Sync Controller III

SDA 9220-5
FRM Delay (subaddress 05)
FRM Disable
Frame display signal FRM enable
Frame display signal FRM disable (FRM = L)
Control Bit FRDIS (D7)
0
1
Delay for Frame
Display Signal
0 LL1.5 cycles
to
127 LL1.5 cycles
FRD 6
(D6)
0
FRD 5
(D5)
0
Control Bit
FRD 4 FRD 3 FRD 2
(D4)
(D3)
(D2)
0
0
0
FRD 1
(D1)
0
FRD 0
(D0)
0
1
1
1
1
1
1
1
CFH Control (subaddress 06)
CFH Width (H level)
0 halfline
to
15 halflines
CFHW3
(D7)
0
1
Control Bit
CFHW2
(D6)
CFHW1
(D5)
0
0
1
1
CFHW0
(D4)
0
1
CFH Position Before VS
3 halflines
to
18 halflines
CFHP3
(D3)
0
1
Control Bit
CFHP2
(D2)
CFHP1
(D1)
0
0
1
1
CFHP0
(D0)
0
1
Semiconductor Group
127