SDA9220-5 Datasheet, PDF (41/42 Pages) Siemens Semiconductor Group – Memory Sync Controller III

SDA 9220-5
Figure 21
Timing Diagram, CSY-Pulse Sequency
B) Start of TV line 3 (1st field) or 316/266 (2nd field) before standard conversion (50/60 Hz)
C) Start of TV line 3 of each field after standard conversion (100/120 Hz)
*) Alternative
**) Rising edge of CSY comes four LL3X cycles before falling edge of BLN2
Semiconductor Group
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