SDA9220-5 Datasheet, PDF (10/42 Pages) Siemens Semiconductor Group – Memory Sync Controller III

SDA 9220-5
Zoom Control (subaddress 03)
Zoom
Normal
Zoom
Control Bit ZM (D7)
0
1
Vertical Position of Zoomed Detail
Vertical position 0
to
Vertical position 7
ZV 2 (D6)
0
1
Control Bit
ZV 1 (D5)
0
1
ZV 0 (D4)
0
1
Horizontal Position of Zoomed Detail
Horizontal position 0
to
Horizontal position 11
Not defined
x: don’t care
HS2 Phase (subaddress 04)
Switching in 60-Hz Mode (VERT = 1)
858 pixels per line
864 pixels per line
ZH 3 (D3)
0
Control Bit
ZH 2 (D2) ZH 1 (D1)
0
0
ZH 0 (D0)
0
1
0
1
1
1
1
×
×
Control Bit N864 (D7)
0
1
HS2 Phase
0 steps
to
108 steps
HP 6
(D6)
0
1
HP 5
(D5)
0
1
Control Bit
HP 4
(D4)
HP 3
(D3)
HP 2
(D2)
0
0
0
0
1
1
One step corresponds to eight LL1.5 cycles (approx. 300 ns).
HP 1
(D1)
0
0
HP 0
(D0)
0
0
Semiconductor Group
126